SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
This register indicates the source of the interrupt.
If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains pending until the CPU has cleared it. If the INTID field is not 0x0000 (the default) and the IE bit in the CANCTL register is set, the interrupt is active. The interrupt line remains active until the INTID field is cleared by reading the CANSTS register, or until the IE bit in the CANCTL register is cleared.
NOTE
Reading the CAN Status (CANSTS) register clears the CAN Interrupt (CANINT) register, if it is pending.
CANINT is shown in Figure 11-9 and described in Table 11-12.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | INTID | ||||||||||||||||||||||||||||||
| R-0x0 | R-0x0 | ||||||||||||||||||||||||||||||