SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
CAN Transmission Request 1 (CANTXRQ1), offset 0x100
CAN Transmission Request 2 (CANTXRQ2), offset 0x104
The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By reading out these bits, the CPU can check which message object has a transmission request pending. The TXRQST bit of a specific message object can be changed by three sources: (1) the CPU via the CANIFnMCTL register, (2) the message handler state machine after the reception of a remote frame, or (3) the message handler state machine after a successful transmission.
The CANTXRQ1 register contains the TXRQST bits of the first 16 message objects in the message RAM; the CANTXRQ2 register contains the TXRQST bits of the second 16 message objects.
CANTXRQn is shown in Figure 11-20 and described in Table 11-23.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TXRQST | ||||||||||||||||||||||||||||||
| R-0x0 | R-0x0 | ||||||||||||||||||||||||||||||