SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
CONTROL is shown in Figure 1-12 and described in Table 1-13.
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The CONTROL register controls the stack used and the privilege level for software execution when the processor is in thread mode, and indicates whether the FPU state is active. This register is only accessible in privileged mode.
Handler mode always uses the MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in handler mode. The exception entry and return mechanisms automatically update the CONTROL register based on the EXC_RETURN value (see Table 1-20). In an OS environment, threads running in thread mode should use the process stack and the kernel and exception handlers should use the main stack. By default, thread mode uses the MSP. To switch the stack pointer used in thread mode to the PSP, either use the MSR instruction to set the ASP bit, as detailed in the Cortex-M4 instruction set chapter in the Arm® Cortex-M4 Devices Generic User Guide, or perform an exception return to thread mode with the appropriate EXC_RETURN value, as shown in Table 1-20.
NOTE
When changing the stack pointer, software must use an ISB instruction immediately after the MSR instruction, ensuring that instructions after the ISB execute use the new stack pointer. See the Cortex-M4 instruction set chapter in the Arm® Cortex-M4 Devices Generic User Guide.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FPCA | ASP | TMPL | ||||
| R-0h | R/W-0h | R/W-0h | R/W-0h | ||||