SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Figure 1-3 shows the Cortex-M4F register set. Table 1-2 lists the Core registers. The core registers are not memory mapped and are accessed by register name, so the base address is n/a (not applicable) and there is no offset.
| Acronym | Register Name | Section |
|---|---|---|
| R_0 to R_12 | Cortex General-Purpose Register 0 to Cortex General-Purpose Register 12 | Section 1.4.2.1.1 |
| SP | Stack Pointer | Section 1.4.2.1.2 |
| LR | Link Register | Section 1.4.2.1.3 |
| PC | Program Counter | Section 1.4.2.1.4 |
| PSR | Program Status Register | Section 1.4.2.1.5 |
| PRIMASK | Priority Mask Register | Section 1.4.2.1.6 |
| FAULTMASK | Fault Mask Register | Section 1.4.2.1.7 |
| BASEPRI | Base Priority Mask Register | Section 1.4.2.1.8 |
| CONTROL | Control Register | Section 1.4.2.1.9 |
| FPSC | Floating-Point Status Control | Section 1.4.2.1.10 |
NOTE
The register type shown in the register descriptions refers to type during program execution in thread mode and handler mode. Debug access can differ.
Complex bit access types are encoded to fit into small table cells. Table 1-3 lists the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |