SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
FAULTMASK is shown in Figure 1-10 and described in Table 1-11.
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The FAULTMASK register prevents activation of all exceptions except for the nonmaskable interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register. See the Cortex-M4 instruction set chapter in the Arm® Cortex-M4 Devices Generic User Guide for more information on these instructions. For more information on exception priority levels, see Section 1.6.2.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0h | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0h | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0h | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | FAULTMASK | ||||||
| R-0h | R/W-0h | ||||||