SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
This section lists and describes the DES µDMA registers, in numerical order by address offset. Registers in this section are relative to the base address of 0x44030000.
Table 14-23 lists the memory-mapped registers for the DES_UDMA. All register offset addresses not listed in Table 14-23 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x30 | DES_DMAIM | DES DMA Interrupt Mask | Section 14.8.1 |
| 0x34 | DES_DMARIS | DES DMA Raw Interrupt Status | Section 14.8.2 |
| 0x38 | DES_DMAMIS | DES DMA Masked Interrupt Status | Section 14.8.3 |
| 0x3C | DES_DMAIC | DES DMA Interrupt Clear | Section 14.8.4 |
Complex bit access types are encoded to fit into small table cells. Table 14-24 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |