22.3.8 DMA

The µDMA model is designed to support both normal µDMA operation on write or read, as well as scatter-gather operation. The normal mode of operation allows for continued writes of byte, half-word, or word (three-byte size is not supported by µDMA for repeated operation) as well as continued reads by byte, half-word, or word. Additionally, the first transaction may be started with a reset.

The 1-Wire DMA Control (ONEWIREDMA) register is used to configure the µDMA. To use µDMA with 1-Wire transmits:

1. Select 1-Wire to use µDMA by programming the DMA Channel Map Select n (DMACHMAPn) register in the µDMA. See for more information.
2. Configure the µDMA to transfer bytes, half-words, or words from memory to the 1-Wire ONEWIREDATW register or from the ONEWIREDATR register through the DMA Channel Control Word (DMACHCTL) register (see ).
3. Set the SZ field of the ONEWIRECS register to byte, half-word, or word (0, 1, or 3). This is the only field programmed in the ONEWIRECS register.
4. Enable the DMA completion interrupt in the ONEWIREIM register. It is also recommended that the ERR and NOATR interrupts should be enabled when using the µDMA to ensure that the application is notified if the reset or transaction failed.
5. Write the DMAOP field of the ONEWIREDMA register with the encoding 0x2 to enable the 1-Wire module assert a µDMA request when ONEWIREDATW is empty. The RST bit in the ONEWIREDMA register can be set for reset to be asserted first before requesting a µDMA access.
6. When the µDMA transfer is complete, the DMA bit in the 1-Wire Raw Interrupt Status (ONEWIRERIS) register is set and the ONEWIREDMA register is cleared.

A 1-Wire µDMA receive configuration is as follows:

1. Select 1-Wire to use µDMA by programming the DMA Channel Map Sellect n (DMACHMAPn) register in the µDMA. See for more information.
2. Configure the µDMA to transfer bytes, half-words, or words from the 1-Wire ONEWIREDATR register through the DMA Channel Control Word (DMACHCTL) register (see ).
3. Enable the DMA completion interrupt in the ONEWIREIM register. It is also recommended that the ERR and NOATR interrupts should be enabled when using the µDMA to ensure that the application is notified if the reset or transaction failed.
4. Write the DMAOP field of the ONEWIREDMA register with the encoding 0x1 or 0x3 to enable a read or read multiple by the µDMA. The RST bit in the ONEWIREDMA register can be set for reset to be asserted first before requesting a µDMA access.
5. Write the ONEWIREDATW register with 0xFFFF.FFFF to prime the read operations. If the RST bit is not set in the ONEWIREDMA register, the transaction begins. If RST was set, the read starts when reset is complete. At the end of the read operation, the µDMA receives a request to transfer the data from the ONEWIREDATR register. If the DMAOP bit was configured for a multiple read (0x3), then the next read transaction will automatically start. If not, then no further µDMA requests occur unless ONEWIREDATR is written to.
6. When a µDMA receive is complete, the DMA bit in the 1-Wire Raw Interrupt Status (ONEWIRERIS) register is set and the ONEWIREDMA register is cleared.

The normal flow for writing and reading in one operation is:

1. Configure the DMAOP bit in the ONEWIREDMA register for a read, and optionally set the RST bit. If RST is selected, the reset is performed first, else the module waits for the next step.
2. Write the ONEWIREDATW register with one, two, or four bytes containing the mix of writes and reads. For example, to write 0x46, 0x20, and then read 2 bytes, set size to word (SZ = 3) and write ONEWIREDATW with 0xFFFF2046 to send the 0x46 and 0x20 and then read the last two bytes. On completion, the ONEWIREDATR contains the read values in the upper two bytes. If RST is not set in the ONEWIREDMA register, the transaction starts. If RST is set, the transaction starts when reset completes. At the end of the operation, the µDMA is requested to transfer the data from the ONEWIREDATR register (read).
3. When the µDMA is done, the DMA bit in the ONEWIRERIS register is set, allowing interrupt on completion by µDMA, and the ONEWIREDMA register is cleared.

It is recommended to enable trigger interrupts for ERR and NOATR when using µDMA so application is notified if reset or the transaction failed.

The natural model for using scatter-gather is:

1. Enable peripheral-scatter-gather in the µDMA module by programming the DMA Channel Control Word (DMACHCTL) register.
2. Set the DMAOP to read (not read multiple) and enable scatter gather in the 1-Wire module by setting the SG bit to 0x1 in the ONEWIREDMA register. This allows use of ONEWDATW register to push through transactions, with µDMA request being triggered off completion, except for the first transaction.
3. Scatter gather can then use a combination of write and read as needed.