| 31-22 |
RESERVED |
R |
0x0 |
|
| 21 |
WRHIGH |
R/W |
0x0 |
CS3n WRITE Strobe Polarity. This field is used if the CSBAUD bit is enabled in EPIHB16CFG2.
0x0 = The WRITE strobe for CS3n accesses is WRn (active Low).
0x1 = The WRITE strobe for CS3n accesses is WR (active High).
|
| 20 |
RDHIGH |
R/W |
0x0 |
CS3n READ Strobe Polarity. This field is used if the CSBAUD bit is enabled in EPIHB16CFG2.
0x0 = The READ strobe for CS3n accesses is RDn (active Low).
0x1 = The READ strobe for CS3n accesses is RD (active High).
|
| 19 |
ALEHIGH |
R/W |
0x1 |
CS3n ALE Strobe Polarity This field is used if the CSBAUD bit is enabled in EPIHB16CFG2.
0x0 = The address latch strobe for CS3n accesses is ADVn (active Low).
0x1 = The address latch strobe for CS3n accesses is ALE (active High).
|
| 18 |
WRCRE |
R/W |
0x0 |
CS3n PSRAM Configuration Register Write. Used for PSRAM configuration registers.
With WRCRE set, the next transaction by the EPI will be a write of the CR bit field in the EPIHBPSRAM register to the configuration register (CR) of the PSRAM.
The WRCRE bit will self clear once the write-enabled CRE access is complete.
0x0 = No Action.
0x1 = Start CRE write transaction for CS3n.
|
| 17 |
RDCRE |
R/W |
0x0 |
CS3n PSRAM Configuration Register Read. Used for PSRAM configuration registers.
With the RDCRE set, the next access is a read of the PSRAM's Configuration Register (CR).
This bit self clears once the CRE access is complete.
The address for the CRE access is located at EPIHBPSRAM
[19:18].
The read data is returned on EPIHBPSRAM
[15:0].
0x0 = No Action.
0x1 = Start CRE read transaction for CS3n.
|
| 16 |
BURST |
R/W |
0x0 |
CS3n Burst Mode. Burst mode must be used with an ALE, which is configured by programming the CSCFG and CSCFGEXT fields in the EPIHB16CFG2 register.
Burst mode must be used in ADMUX, which is set by the MODE field in EPIHB16CFG4.
Burst mode is optimized for word-length accesses.
0x0 = Burst mode is disabled.
0x1 = Burst mode is enabled for CS3n.
|
| 15-8 |
RESERVED |
R |
0x0 |
|
| 7-6 |
WRWS |
R/W |
0x0 |
CS3n Write Wait States. This field adds wait states to the data phase of CS2n accesses (the address phase is not affected).
The effect is to delay the rising edge of WRn (or the falling edge of WR).
Each wait state adds 2 EPI clock cycles to the access time.
The WRWSM bit in the EPIHB16TIME4 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
This field is used if the CSBAUD bit is set in the EPIHB16CFG2 register.
This field is not applicable in BURST mode.
This field is used in conjunction with the EPIBAUD2 register.
0x0 = Active WRn is 2 EPI clocks
0x1 = Active WRn is 4 EPI clocks
0x2 = Active WRn is 6 EPI clocks
0x3 = Active WRn is 8 EPI clocks
|
| 5-4 |
RDWS |
R/W |
0x0 |
CS3n Read Wait States. This field adds wait states to the data phase of CS3n accesses (the address phase is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD).
Each wait state adds 2 EPI clock cycles to the access time.
The RDWSM bit in the EPIHB16TIME4 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
This field is used when the CSBAUD bit is set in the EPIHB16CFG2 register.
This field is not applicable in BURST mode.
This field is used in conjunction with the EPIBAUD2 register.
0x0 = Active RDn is 2 EPI clocks
0x1 = Active RDn is 4 EPI clocks
0x2 = Active RDn is 6 EPI clocks
0x3 = Active RDn is 8 EPI clocks
|
| 3-2 |
RESERVED |
R |
0x0 |
|
| 1-0 |
MODE |
R/W |
0x0 |
CS3n Host Bus Sub-Mode. This field determines which Host Bus 16 sub-mode to use for CS3n in multiple chip select mode.
Sub-mode use is determined by the connected external peripheral.
See for information on how this bit field affects the operation of the EPI signals.
The CSBAUD bit must be set to enable this CS3n MODE field.
If CSBAUD is clear, all chip-selects use the MODE configuration defined in the EPIHB16CFG register.
0x0 = reserved
0x1 = ADNONMUX - D[15:0]Data and address are separate. This mode is not practical in HB16 mode for normal peripherals because there are generally not enough address bits available.
|