SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 16-12 lists the memory-mapped registers for the EPI. All register offset addresses not listed in Table 16-12 should be considered as reserved locations and the register contents should not be modified.
The EPI controller clock must be enabled before the registers can be programmed (see Section 4.2.89). There must be a delay of 3 system clocks after the EPI module clock is enabled before any EPI module registers are accessed.
NOTE
A write immediately followed by a read of the same register may not return correct data. A delay (instruction or NOP) must be inserted between the write and the read for correct operation. Read-write does not have this issue, so use of read-write for clear of error interrupt cause is not affected.
NOTE
For all versions of EPI, only WORD read and write accesses to registers are supported.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x000 | EPICFG | EPI Configuration | Section 16.5.1 |
| 0x004 | EPIBAUD | EPI Main Baud Rate | Section 16.5.2 |
| 0x008 | EPIBAUD2 | EPI Main Baud Rate | Section 16.5.3 |
| 0x010 | EPISDRAMCFG | EPI SDRAM Configuration | Section 16.5.4 |
| 0x010 | EPIHB8CFG | EPI Host-Bus 8 Configuration | Section 16.5.5 |
| 0x010 | EPIHB16CFG | EPI Host-Bus 16 Configuration | Section 16.5.6 |
| 0x010 | EPIGPCFG | EPI General-Purpose Configuration | Section 16.5.7 |
| 0x014 | EPIHB8CFG2 | EPI Host-Bus 8 Configuration 2 | Section 16.5.8 |
| 0x014 | EPIHB16CFG2 | EPI Host-Bus 16 Configuration 2 | Section 16.5.9 |
| 0x01C | EPIADDRMAP | EPI Address Map | Section 16.5.10 |
| 0x020 | EPIRSIZE0 | EPI Read Size 0 | Section 16.5.11 |
| 0x024 | EPIRADDR0 | EPI Read Address 0 | Section 16.5.12 |
| 0x028 | EPIRPSTD0 | EPI Non-Blocking Read Data 0 | Section 16.5.13 |
| 0x030 | EPIRSIZE1 | EPI Read Size 1 | Section 16.5.11 |
| 0x034 | EPIRADDR1 | EPI Read Address 1 | Section 16.5.12 |
| 0x038 | EPIRPSTD1 | EPI Non-Blocking Read Data 1 | Section 16.5.13 |
| 0x060 | EPISTAT | EPI Status | Section 16.5.14 |
| 0x06C | EPIRFIFOCNT | EPI Read FIFO Count | Section 16.5.15 |
| 0x70 to 0x8C | EPIREADFIFO0 to EPIREADFIFO7 | EPI Read FIFO 0 to EPI Read FIFO 7 | Section 16.5.16 |
| 0x200 | EPIFIFOLVL | EPI FIFO Level Selects | Section 16.5.17 |
| 0x24 | EPIWFIFOCNT | EPI Write FIFO Count | Section 16.5.18 |
| 0x28 | EPIDMATXCNT | EPI DMA Transmit Count | Section 16.5.19 |
| 0x210 | EPIIM | EPI Interrupt Mask | Section 16.5.20 |
| 0x214 | EPIRIS | EPI Raw Interrupt Status | Section 16.5.21 |
| 0x218 | EPIMIS | EPI Masked Interrupt Status | Section 16.5.22 |
| 0x21C | EPIEISC | EPI Error and Interrupt Status and Clear | Section 16.5.23 |
| 0x308 | EPIHB8CFG3 | EPI Host-Bus 8 Configuration 3 | Section 16.5.24 |
| 0x308 | EPIHB16CFG3 | EPI Host-Bus 16 Configuration 3 | Section 16.5.25 |
| 0x30C | EPIHB8CFG4 | EPI Host-Bus 8 Configuration 4 | Section 16.5.26 |
| 0x30C | EPIHB16CFG4 | EPI Host-Bus 16 Configuration 4 | Section 16.5.27 |
| 0x310 | EPIHB8TIME | EPI Host-Bus 8 Timing Extension | Section 16.5.28 |
| 0x310 | EPIHB16TIME | EPI Host-Bus 16 Timing Extension | Section 16.5.29 |
| 0x314 | EPIHB8TIME2 | EPI Host-Bus 8 Timing Extension | Section 16.5.30 |
| 0x314 | EPIHB16TIME2 | EPI Host-Bus 16 Timing Extension | Section 16.5.31 |
| 0x318 | EPIHB8TIME3 | EPI Host-Bus 8 Timing Extension | Section 16.5.32 |
| 0x318 | EPIHB16TIME3 | EPI Host-Bus 16 Timing Extension | Section 16.5.33 |
| 0x31C | EPIHB8TIME4 | EPI Host-Bus 8 Timing Extension | Section 16.5.34 |
| 0x31C | EPIHB16TIME4 | EPI Host-Bus 16 Timing Extension | Section 16.5.35 |
| 0x360 | EPIHBPSRAM | EPI Host-Bus PSRAM | Section 16.5.36 |
Complex bit access types are encoded to fit into small table cells. Table 16-13 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |