16.5.30 EPIHB8TIME2 Register (Offset = 0x314) [reset = 0xA000]
EPI Host-Bus 8 Timing Extension (EPIHB8TIME2)
NOTE
The MODE field in the EPICFG register determines which configuration is enabled.
For EPIHB8TIME2 to be valid, the MODE field must be 0x2.
EPIHB8TIME2 is shown in Figure 16-59 and described in Table 16-43.
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Figure 16-59 EPIHB8TIME2 Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
IRDYDLY |
| R-0x0 |
R/W-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| reserved-1 |
| R-0x2 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| reserved-1 |
CAPWIDTH |
RESERVED |
| R-0x2 |
R/W-0x2 |
R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
WRWSM |
RESERVED |
RDWSM |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
Table 16-43 EPIHB8TIME2 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-26 |
RESERVED |
R |
0x0 |
|
| 25-24 |
IRDYDLY |
R/W |
0x0 |
CS1n Input Ready Delay
0x0 = reserved
0x1 = Stall begins one EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
0x2 = Stall begins two EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
0x3 = Stall begins three EPI clocks past iRDY low being sampled on the rising edge of EPIO clock.
|
| 23-14 |
RESERVED |
R |
0x2 |
|
| 13-12 |
CAPWIDTH |
R/W |
0x2 |
CS1n Inter-transfer Capture Width Controls the delay between Host-Bus transfers.
0x0 = Reserved
0x1 = 1 EPI clock.
0x2 = 2 EPI clock.
0x3 = Reserved
|
| 11-5 |
RESERVED |
R |
0x0 |
|
| 4 |
WRWSM |
R/W |
0x0 |
CS1n Write Wait State Minus One This bit is used with the WRWS field in EPIHB8CFG2.
This field is not applicable in BURST mode.
0x0 = No change in the number of wait state clock cycles programmed in the in WRWS field in EPIHB8CFG2 register.
0x1 (Write) = Wait state value is noWRWS; 1WRWS field is programmed in EPIHB8CFG2.
|
| 3-1 |
RESERVED |
R |
0x0 |
|
| 0 |
RDWSM |
R/W |
0x0 |
CS1n Read Wait State Minus One This field is used with RDWS field in EPIHB8CFG2.
This bit is not applicable in BURST mode.
0x0 = No change in the number of wait state clock cycles programmed in the RDWS field of EPIHB8CFG2.
0x1 (Write) = Wait state value is noRDWS – 1RDWS field is programmed in EPIHB8CFG2.
|