SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
EPI Read Size 0 (EPIRSIZE0), offset 0x020
EPI Read Size 1 (EPIRSIZE1), offset 0x030
This register selects the size of transactions when performing non-blocking reads with the EPIRPSTDn registers. This size affects how the external address is incremented.
The SIZE field must match the external data width as configured in the EPIHBnCFG or EPIGPCFG register.
SDRAM mode uses a 16-bit data interface. If SIZE is 0x1, data is returned on the least significant bits (D[7:0]), and the remaining bits D[31:8] are all zeros, therefore the data on bits D[15:8] is lost. If SIZE is 0x2, data is returned on the least significant bits (D[15:0]), and the remaining bits D[31:16] are all zeros.
Note that changing this register while a read is active has an unpredictable effect.
EPIRSIZEn is shown in Figure 16-40 and described in Table 16-24.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||||||||||
| R-0x0 | |||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SIZE | ||||||||||||||
| R-0x0 | R/W-0x3 | ||||||||||||||