| 31-22 |
RESERVED |
R |
0x0 |
|
| 21 |
WRHIGH |
R/W |
0x0 |
CS3n WRITE Strobe Polarity. This field is used if the CSBAUD bit is enabled in EPIHB8CFG2.
0x0 = The WRITE strobe for CS3n accesses is WRn (active low).
0x1 = The WRITE strobe for CS3n accesses is WR (active high).
|
| 20 |
RDHIGH |
R/W |
0x0 |
CS2n READ Strobe Polarity. This field is used if the CSBAUD bit is enabled in EPIHB8CFG2.
0x0 = The READ strobe for CS3n accesses is RDn (active low).
0x1 = The READ strobe for CS3n accesses is RD (active high).
|
| 19 |
ALEHIGH |
R/W |
0x1 |
CS3n ALE Strobe Polarity. This field is used if the CSBAUD bit is enabled in EPIHB8CFG2
0x0 = The address latch strobe for CS3n accesses is ADVn (active low).
0x1 = The address latch strobe for CS3n accesses is ALE (active high).
|
| 18-8 |
RESERVED |
R |
0x0 |
|
| 7-6 |
WRWS |
R/W |
0x0 |
CS3n Write Wait States. This field adds wait states to the data phase of CS3n accesses (the address phase is not affected).
The effect is to delay the rising edge of WRn (or the falling edge of WR).
Each wait state adds 2 EPI clock cycles to the access time.
The WRWSM bit in the EPIHB8TIME4 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
This field is used if the CSBAUD bit is enabled in the EPIHB8CFG2 register.
This field is not applicable in BURST mode.
This field is used in conjunction with the EPIBAUD2 register.
0x0 = Active WRn is 2 EPI clocks
0x1 = Active WRn is 4 EPI clocks
0x2 = Active WRn is 6 EPI clocks
0x3 = Active WRn is 8 EPI clocks
|
| 5-4 |
RDWS |
R/W |
0x0 |
CS3n Read Wait States. This field adds wait states to the data phase of CS3n accesses (the address phase is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD).
Each wait state adds 2 EPI clock cycles to the access time.
The RDWSM bit in the EPIHB8TIME4 register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
This field is used when the CSBAUD bit is set in the EPIHB8CFG2 register.
This field is not applicable in BURST mode.
This field is used in conjunction with the EPIBAUD2 register.
0x0 = Active RDn is 2 EPI clocks
0x1 = Active RDn is 4 EPI clocks
0x2 = Active RDn is 6 EPI clocks
0x3 = Active RDn is 8 EPI clocks
|
| 3-2 |
RESERVED |
R |
0x0 |
|
| 1-0 |
MODE |
R/W |
0x0 |
CS3n Host Bus Sub-Mode. This field determines which Host Bus 8 sub-mode to use for CS3n in multiple chip select mode.
Sub-mode use is determined by the connected external peripheral.
See for information on how this bit field affects the operation of the EPI signals.
The CSBAUD bit must be set to enable this CS3n MODE field.
If CSBAUD is clear, all chip-selects use the MODE configuration defined in the EPIHB8CFG register.
0x0 = reserved
0x1 = ADNONMUX - D[7:0]Data and address are separate.
|