16.5.4 EPISDRAMCFG Register (Offset = 0x10) [reset = 0x82EE0000]
EPI SDRAM Configuration (EPISDRAMCFG)
NOTE
The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014.
To access EPISDRAMCFG, the MODE field must be 0x1.
The SDRAM Configuration register is used to specify several parameters for the SDRAM controller. Note that this register is reset when the MODE field in the EPICFG register is changed. If another mode is selected and the SDRAM mode is selected again, the values must be reinitialized.
The SDRAM interface is designed to interface to x16 SDR SDRAMs of 64 MHz or higher, with the address and data pins overlapped (wire ORed on the board). See Table 16-2 for pin assignments.
EPISDRAMCFG is shown in Figure 16-33 and described in Table 16-17.
Return to Summary Table.
Figure 16-33 EPISDRAMCFG Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| FREQ |
RESERVED |
RFSH |
| R/W-0x2 |
R-0x0 |
R/W-0x2EE |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RFSH |
| R/W-0x2EE |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
SLEEP |
RESERVED |
| R-0x0 |
R/W-0x0 |
R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
SIZE |
| R-0x0 |
R/W-0x0 |
|
Table 16-17 EPISDRAMCFG Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-30 |
FREQ |
R/W |
0x2 |
EPI Frequency Range.
This field configures the frequency range used for delay references by internal counters. This EPI frequency is the system frequency with the divider programmed by the COUNT0 bit in the EPIBAUDn register bit.
This field affects the power up, precharge, and auto refresh delays. This field does not affect the refresh counting, which is configured separately using the RFSH field (and is based on system clock rate and number of rows per bank).
The ranges are:
0x0 = 0 to 15 MHz
0x1 = 15 to 30 MHz
0x2 = 30 to 50 MHz
0x3 = 50 to 100 MHz
|
| 29-27 |
RESERVED |
R |
0x0 |
|
| 26-16 |
RFSH |
R/W |
0x2EE |
Refresh Counter
This field contains the refresh counter in EPI clocks.
The reset value of 0x2EE provides a refresh period of 64 ms when using a 50 MHz EPI clock. |
| 15-10 |
RESERVED |
R |
0x0 |
|
| 9 |
SLEEP |
R/W |
0x0 |
Sleep Mode
0x0 = No effect.
0x1 = The SDRAM is put into low power state, but is self-refreshed.
|
| 8-2 |
RESERVED |
R |
0x0 |
|
| 1-0 |
SIZE |
R/W |
0x0 |
Size of SDRAM
The value of this field affects address pins and behavior.
0x0 = 64 megabits (8MB)
0x1 = 128 megabits (16MB)
0x2 = 256 megabits (32MB)
0x3 = 512 megabits (64MB)
|