16.5.5 EPIHB8CFG Register (Offset = 0x10) [reset = 0x0008FF00]
EPI Host-Bus 8 Configuration (EPIHB8CFG)
NOTE
The MODE field in the EPICFG register determines which configuration register is accessed for offsets 0x010 and 0x014.
To access EPIHB8CFG, the MODE field must be 0x2.
The Host Bus 8 Configuration register is activated when the HB8 mode is selected. The HB8 mode supports muxed address/data (overlay of lower 8 address and all 8 data pins), separate address/data, and address-less FIFO mode. Note that this register is reset when the MODE field in the EPICFG register is changed. If another mode is selected and the HB8 mode is selected again, the values must be reinitialized.
This mode is intended to support SRAMs, Flash memory (read), FIFOs, CPLDs/FPGAs, and devices with an MCU/HostBus slave or 8-bit FIFO interface support.
Refer to Table 16-7 for information on signal configuration controlled by this register and the EPIHB8CFG2 register.
If less address pins are required, the corresponding AFSEL bit (Section 17.5.10) should not be enabled so the EPI controller does not drive those pins, and they are available as standard GPIOs.
EPI Host-Bus 8 Mode can be configured to use one to four chip selects with and without the use of ALE. If an alternative to chip selects are required, a chip enable can be handled in one of three ways:
- Manually control via GPIOs.
- Associate one or more upper address pins to CE. Because CE is normally CEn, lower addresses are not used. For example, if pins EPI0S27 and EPI0S26 are used for Device 1 and 0 respectively, then address 0x68000000 accesses Device 0 (Device 1 has its CEn high), and 0x64000000 accesses Device 1 (Device 0 has its CEn high). The pull-up behavior on the corresponding GPIOs must be properly configured to ensure that the pins are disabled when the interface is not in use.
- With certain SRAMs, the ALE can be used as CEn because the address remains stable after the ALE strobe. The subsequent WRn or RDn signals write or read when ALE is low thus providing CEn functionality.
EPIHB8CFG is shown in Figure 16-34 and described in Table 16-18.
Return to Summary Table.
Figure 16-34 EPIHB8CFG Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| CLKGATE |
CLKGATEI |
CLKINV |
RDYEN |
IRDYINV |
RESERVED |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| XFFEN |
XFEEN |
WRHIGH |
RDHIGH |
ALEHIGH |
RESERVED |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x1 |
R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| MAXWAIT |
| R/W-0xFF |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| WRWS |
RDWS |
RESERVED |
MODE |
| R/W-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
Table 16-18 EPIHB8CFG Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
CLKGATE |
R/W |
0x0 |
Clock Gated
A software application should only set the CLKGATE bit when there are no pending transfers or no EPI register access has been issued.
0x0 = The EPI clock is free running.
0x1 = The EPI clock is held low.
|
| 30 |
CLKGATEI |
R/W |
0x0 |
Clock Gated when Idle
Note that EPI0S32 is an iRDY signal if RDYEN is set.
CLKGATEI is ignored if CLKPIN is 0 or if the COUNT0 field in the EPIBAUD register is cleared.
0x0 = The EPI clock is free running.
0x1 = The EPI clock is output only when there is data to write or read (current transaction); otherwise the EPI clock is held low.
|
| 29 |
CLKINV |
R/W |
0x0 |
Invert Output Clock Enable
0x0 = No effect.
0x1 = Invert EPI clock to ensure the rising edge is centered for outbound signal's setup and hold. Inbound signal is captured on rising edge EPI clock.
|
| 28 |
RDYEN |
R/W |
0x0 |
Input Ready Enable
0x0 = No effect.
0x1 = An external ready can be used to control the continuation of the current access. If this bit is set and the iRDY signal (EPIS032) is low, the current access is stalled.
|
| 27 |
IRDYINV |
R/W |
0x0 |
Input Ready Invert
0x0 = No effect.
0x1 = Invert the polarity of incoming external ready (iRDY signal). If this bit is set and the iRDY signal (EPIS032) is high the current access is stalled.
|
| 26-24 |
RESERVED |
R |
0x0 |
|
| 23 |
XFFEN |
R/W |
0x0 |
External FIFO FULL Enable
0x0 = No effect.
0x1 = An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL full signal is high, XFIFO writes are stalled.
|
| 22 |
XFEEN |
R/W |
0x0 |
External FIFO EMPTY Enable
0x0 = No effect.
0x1 = An external FIFO empty signal can be used to control read cycles. If this bit is set and the FEMPTY signal is high, XFIFO reads are stalled.
|
| 21 |
WRHIGH |
R/W |
0x0 |
WRITE Strobe Polarity
0x0 = The WRITE strobe for CS0n is WRn (active Low).
0x1 = The WRITE strobe for CS0n is WR (active High).
|
| 20 |
RDHIGH |
R/W |
0x0 |
READ Strobe Polarity
0x0 = The READ strobe for CS0n is RDn (active Low).
0x1 = The READ strobe for CS0n is RD (active High).
|
| 19 |
ALEHIGH |
R/W |
0x1 |
ALE Strobe Polarity
0x0 = The address latch strobe for CS0n accesses is ALEn (active Low).
0x1 = The address latch strobe for CS0n accesses is ALE (active High).
|
| 18-16 |
RESERVED |
R |
0x0 |
|
| 15-8 |
MAXWAIT |
R/W |
0xFF |
Maximum Wait
This field defines the maximum number of external clocks to wait while an external FIFO ready signal is holding off a transaction (FFULL and FEMPTY).
When the MAXWAIT value is reached the ERRRIS interrupt status bit is set in the EPIRIS register.
When this field is clear, the transaction can be held off forever without a system interrupt.
When the MODE field is configured to be 0x2 and the BLKEN bit is set in the EPICFG register, enabling HB8 mode, this field defaults to 0xFF. |
| 7-6 |
WRWS |
R/W |
0x0 |
Write Wait States
This field adds wait states to the data phase of CS0n (the address phase is not affected).
The effect is to delay the rising edge of WRn (or the falling edge of WR).
Each wait state adds 2 EPI clock cycles to the access time.
The WRWSM bit in the EPIHB8TIME register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
This field is not applicable in BURST mode.
This field is used in conjunction with the EPIBAUD register.
0x0 = Active WRn is 2 EPI clocks.
0x1 = Active WRn is 4 EPI clocks.
0x2 = Active WRn is 6 EPI clocks.
0x3 = Active WRn is 8 EPI clocks.
|
| 5-4 |
RDWS |
R/W |
0x0 |
Read Wait States
This field adds wait states to the data phase of CS0n (the address phase is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD).
Each wait state adds 2 EPI clock cycles to the access time.
The RDWSM bit in the EPIHB8TIME register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
This field is not applicable in BURST mode.
This field is used in conjunction with the EPIBAUD register
0x0 = Active RDn is 2 EPI clocks.
0x1 = Active RDn is 4 EPI clocks.
0x2 = Active RDn is 6 EPI clocks.
0x3 = Active RDn is 8 EPI clocks.
|
| 3-2 |
RESERVED |
R |
0x0 |
|
| 1-0 |
MODE |
R/W |
0x0 |
Host Bus Sub-Mode
This field determines which of four Host Bus 8 sub-modes to use.
Sub-mode use is determined by the connected external peripheral.
See for information on how this bit field affects the operation of the EPI signals.
When used with multiple chip select option and the CSBAUD bit is set to 1 in the EPIHB8CFG2 register, this configuration is for CS0n.
If the multiple chip select option is enabled and CSBAUD is clear, all chip-selects use the MODE encoding programmed in this register.
0x0 = ADMUX - AD[7:0]. Data and Address are muxed.
0x1 = ADNONMUX - D[7:0]. Data and address are separate.
0x2 = Continuous Read - D[7:0]. This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OEn strobing.
0x3 = XFIFO - D[7:0]. This mode adds XFIFO controls with sense of XFIFO full and XFIFO empty. This mode uses no address or ALE. The XFIFO can only be used in asynchronous mode.
|