Chip Select Extended Configuration

This field is used in conjunction with CSCFG, to extend the chip select options, and ALE format. The values 0x0 through 0x3 are from the CSCFG field. The CSCFGEXT bit extends the values to 0x7.

0x0 = CSCFG bit field is used in chip select configuration.

0x1 = The CSCFG bit field is extended with CSCFGEXT representing the MSB.

The possible chip select configurations (CSCFGEXT + CSCFG encodings) when the CSCFGEXT bit is enabled are:

0x0 = ALE Configuration. EPI0S30 is used as an address latch (ALE). The ALE signal is generally used when the address and data are muxed (MODE field in the EPIHB8CFG register is 0x0). The ALE signal is used by an external latch to hold the address through the bus cycle.

0x1 = CSn Configuration. EPI0S30 is used as a Chip Select (CSn). When using this mode, the address and data are generally not muxed (MODE field in the EPIHB8CFG register is 0x1). However, if address and data muxing is needed, the WR signal (EPI0S29) and the RD signal (EPI0S28) can be used to latch the address when CSn is low.

0x2 = Dual CSn Configuration. EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map. This configuration can be used for a RAM bank split between 2 devices as well as when using both an external RAM and an external peripheral.

0x3 = ALE with Dual CSn Configuration. EPI0S30 is used as address latch (ALE), EPI0S27 is used as CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map.

0x4 = ALE with Single CSn Configuration. EPI0S30 is used as address latch (ALE) and EPI0S27 is used as CSn.

0x5 = Quad CSn Configuration. EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. EPI0S34 is used as CS2n and EPI0S33 is used as CS3n.

0x6 = ALE with Quad CSn Configuration. EPI0S30 is used as ALE, EPI0S26 is CS0n, and EPI0S27 is used as CS1n. EPI0S34 is used as CS2n and EPI0S33 is used as CS3n.

0x7 = Reserved

0x0 = Same Baud Rate and Same Sub-ModeAll CSn use the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register and the sub-mode programmed in the MODE field of the EPIHB8CFG register.

0x1 = Different Baud RatesCS0n uses the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD register. CS1n uses the baud rate defined by the COUNT1 field in the EPIBAUD register.CS2n uses the baud rate for the external bus that is defined by the COUNT0 field in the EPIBAUD2 register. CS3n uses the baud rate defined by the COUNT1 field in the EPIBAUD2 register.In addition, the sub-modes for each chip select are individually programmed in their respective EPIHB8CFGn registers.

0x0 = ALE Configuration. EPI0S30 is used as an address latch (ALE). The ALE signal is generally used when the address and data are muxed (HB8MODE field in the EPIHB8CFG register is 0x0). The ALE signal is used by an external latch to hold the address through the bus cycle.

0x1 = CSn Configuration. EPI0S30 is used as a Chip Select (CSn). When using this mode, the address and data are generally not muxed (HB8MODE field in the EPIHB8CFG register is 0x1). However, if address and data muxing is needed, the WR signal (EPI0S29) and the RD signal (EPI0S28) can be used to latch the address when CSn is low.

0x2 = Dual CSn Configuration. EPI0S30 is used as CS0n and EPI0S27 is used as CS1n. Whether CS0n or CS1n is asserted is determined by two methods. If only external RAM or external PER is enabled in the address map, the most significant address bit for a respective external address map controls CS0n or CS1n. If both external RAM and external PER is enabled, CS0n is mapped to PER and CS1n is mapped to RAM. This configuration can be used for a RAM bank split between 2 devices as well as when using both an external RAM and an external peripheral.

0x3 = ALE with Dual CSn Configuration. EPI0S30 is used as address latch (ALE), EPI0S27 is used as CS1n, and EPI0S26 is used as CS0n. Whether CS0n or CS1n is asserted is determined by the most significant address bit for a respective external address map.

CS1n WRITE Strobe Polarity This field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled.

0x0 = The WRITE strobe for CS1n accesses is WRn (active Low).

0x1 = The WRITE strobe for CS1n accesses is WR (active High).

CS1n READ Strobe Polarity This field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled.

0x0 = The READ strobe for CS1n accesses is RDn (active Low).

0x1 = The READ strobe for CS1n accesses is RD (active High).

CS1n ALE Strobe Polarity This field is used if the CSBAUD bit in the EPIHB8CFG2 register is enabled.

0x0 = The address latch strobe for CS1n accesses is ALEn (active Low).

0x1 = The address latch strobe for CS1n accesses is ALE (active High).

0x0 = Active WRn is 2 EPI clocks.

0x1 = Active WRn is 4 EPI clocks

0x2 = Active WRn is 6 EPI clocks

0x3 = Active WRn is 8 EPI clocks

0x0 = Active RDn is 2 EPI clocks

0x1 = Active RDn is 4 EPI clocks

0x2 = Active RDn is 6 EPI clocks

0x3 = Active RDn is 8 EPI clocks

0x0 = reserved

0x1 = ADNONMUX - D[7:0]Data and address are separate.