16.5.20 EPIIM Register (Offset = 0x210) [reset = 0x0]
EPI Interrupt Mask (EPIIM)
This register is the interrupt mask set or clear register. For each interrupt source (read, write, and error), a mask value of 1 allows the interrupt source to trigger an interrupt to the interrupt controller; a mask value of 0 prevents the interrupt source from triggering an interrupt.
EPIIM is shown in Figure 16-49 and described in Table 16-33.
Return to Summary Table.
Figure 16-49 EPIIM Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DMAWRIM |
DMARDIM |
WRIM |
RDIM |
ERRIM |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 16-33 EPIIM Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-5 |
RESERVED |
R |
0x0 |
|
| 4 |
DMAWRIM |
R/W |
0x0 |
Write µDMA Interrupt Mask
0x0 = DMAWRRIS in the EPIRIS register is masked and does not cause an interrupt.
0x1 = DMAWRRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller.
|
| 3 |
DMARDIM |
R/W |
0x0 |
Read µDMA Interrupt Mask
0x0 = DMARDRIS in the EPIRIS register is masked and does not cause an interrupt.
0x1 = DMARDRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller.
|
| 2 |
WRIM |
R/W |
0x0 |
Write FIFO Empty Interrupt Mask
0x0 = WRRIS in the EPIRIS register is masked and does not cause an interrupt.
0x1 = WRRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller.
|
| 1 |
RDIM |
R/W |
0x0 |
Read FIFO Full Interrupt Mask
0x0 = RDRIS in the EPIRIS register is masked and does not cause an interrupt.
0x1 = RDRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller.
|
| 0 |
ERRIM |
R/W |
0x0 |
Error Interrupt Mask
0x0 = ERRIS in the EPIRIS register is masked and does not cause an interrupt.
0x1 = ERRIS in the EPIRIS register is not masked and can trigger an interrupt to the interrupt controller.
|