16.5.22 EPIMIS Register (Offset = 0x218) [reset = 0x0]
EPI Masked Interrupt Status (EPIMIS)
This register is the masked interrupt status register. On read, it gives the current state of each interrupt source (read, write, and error) after being masked via the EPIIM register. A write has no effect.
The values returned are the ANDing of the EPIIM and EPIRIS registers. If a bit is set in this register, the interrupt is sent to the interrupt controller.
EPIMIS is shown in Figure 16-51 and described in Table 16-35.
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Figure 16-51 EPIMIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DMAWRMIS |
DMARDMIS |
WRMIS |
RDMIS |
ERRMIS |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 16-35 EPIMIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-5 |
RESERVED |
R |
0x0 |
|
| 4 |
DMAWRMIS |
R |
0x0 |
Write µDMA Masked Interrupt Status. This bit is cleared by writing a 1 to the DMAWRIC bit in the EPIEISC register.
0x0 = The write µDMA has not completed or the interrupt is masked.
0x1 = The write µDMA has completed and the DMAWRIM bit in the EPIIM register is set, triggering an interrupt to the interrupt controller.
|
| 3 |
DMARDMIS |
R |
0x0 |
Read µDMA Masked Interrupt Status. This bit is cleared by writing a 1 to the DMARDIC bit in the EPIEISC register.
0x0 = The read µDMA has not completed or the interrupt is masked.
0x1 = The read µDMA has completed and the DMAWRIM bit in the EPIIM register is set, triggering an interrupt to the interrupt controller.
|
| 2 |
WRMIS |
R |
0x0 |
Write Masked Interrupt Status
0x0 = The number of available entries in the WFIFO is above the range specified by the trigger level or the interrupt is masked.
0x1 = The number of available entries in the WFIFO is within the range specified by the trigger level (the WRFIFO field in the EPIFIFOLVL register) and the WRIM bit in the EPIIM register is set, triggering an interrupt to the interrupt controller.
|
| 1 |
RDMIS |
R |
0x0 |
Read Masked Interrupt Status
0x0 = The number of valid entries in the NBRFIFO is below the range specified by the trigger level or the interrupt is masked.
0x1 = The number of valid entries in the NBRFIFO is within the range specified by the trigger level (the RDFIFO field in the EPIFIFOLVL register) and the RDIM bit in the EPIIM register is set, triggering an interrupt to the interrupt controller.
|
| 0 |
ERRMIS |
R |
0x0 |
Error Masked Interrupt Status
0x0 = An error has not occurred or the interrupt is masked.
0x1 = A WFIFO Full, a Read Stalled, or a Timeout error has occurred and the ERIM bit in the EPIIM register is set, triggering an interrupt to the interrupt controller.
|