16.5.21 EPIRIS Register (Offset = 0x214) [reset = 0x4]
EPI Raw Interrupt Status (EPIRIS)
This register is the raw interrupt status register. On a read, it gives the current state of each interrupt source. A write has no effect.
Note that raw status for read and write is set or cleared based on FIFO fullness as controlled by EPIFIFOLVL.
Raw status for error is held until the error is cleared by writing to the EPIEISC register.
EPIRIS is shown in Figure 16-50 and described in Table 16-34.
Return to Summary Table.
Figure 16-50 EPIRIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DMAWRRIS |
DMARDRIS |
WRRIS |
RDRIS |
ERRRIS |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x1 |
R-0x0 |
R-0x0 |
|
Table 16-34 EPIRIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-5 |
RESERVED |
R |
0x0 |
|
| 4 |
DMAWRRIS |
R |
0x0 |
Write µDMA Raw Interrupt Status This bit is cleared by writing a 1 to the DMAWRIC bit in the EPIEISC register.
0x0 = The write µDMA has not completed.
0x1 = The write µDMA has completed.
|
| 3 |
DMARDRIS |
R |
0x0 |
Read µDMA Raw Interrupt Status This bit is cleared by writing a 1 to the DMARDIC bit in the EPIEISC register.
0x0 = The read µDMA has not completed.
0x1 = The read µDMA has completed.
|
| 2 |
WRRIS |
R |
0x1 |
Write Raw Interrupt Status This bit is cleared when the level in the WFIFO is above the trigger point programmed by the WRFIFO field.
0x0 = The number of available entries in the WFIFO is above the range specified by the WRFIFO field in the EPIFIFOLVL register.
0x1 = The number of available entries in the WFIFO is within the trigger range specified by the WRFIFO field in the EPIFIFOLVL register.
|
| 1 |
RDRIS |
R |
0x0 |
Read Raw Interrupt Status This bit is cleared when the level in the NBRFIFO is below the trigger point programmed by the RDFIFO field.
0x0 = The number of valid entries in the NBRFIFO is below the trigger range specified by the RDFIFO field in the EPIFIFOLVL register.
0x1 = The number of valid entries in the NBRFIFO is in the trigger range specified by the RDFIFO field in the EPIFIFOLVL register.
|
| 0 |
ERRRIS |
R |
0x0 |
Error Raw Interrupt Stat
Error Raw Interrupt Status
The error interrupt occurs in the following situations:
- WFIFO Full. For a full WFIFO to generate an error interrupt, the WFERR bit in the EPIFIFOLVL register must be set.
- Read Stalled. For a stalled read to generate an error interrupt, the RSERR bit in the EPIFIFOLVL register must be set.
- Timeout. If the MAXWAIT field in the EPIHBnCFG register is configured to a value other than 0, a timeout error occurs when XFIFO not-ready signals hold a transaction for more than the count in the MAXWAIT field.
0x0 = An error has not occurred.
0x1 = A WFIFO Full, a Read Stalled, or a Timeout error has occurred.
To determine which error occurred, read the status of the EPI Error Interrupt Status and Clear (EPIEISC) register. This bit is cleared by writing a 1 to the bit in the EPIEISC register that caused the interrupt.
|