16.5.14 EPISTAT Register (Offset = 0x60) [reset = 0x0]
EPI Status (EPISTAT)
This register indicates which non-blocking read register is currently active; it also indicates whether the external interface is busy performing a write or non-blocking read (it cannot be performing a blocking read, as the bus would be blocked and as a result, this register could not be accessed).
This register is useful to determining which non-blocking read register is active when both are loaded with values and when implementing sequencing or sharing.
This register is also useful when canceling non-blocking reads, as it shows how many values were read by the canceled side.
EPISTAT is shown in Figure 16-43 and described in Table 16-27.
Return to Summary Table.
Figure 16-43 EPISTAT Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
XFFULL |
| R-0x0 |
R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| XFEMPTY |
INITSEQ |
WBUSY |
NBRBUSY |
RESERVED |
ACTIVE |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 16-27 EPISTAT Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-9 |
RESERVED |
R |
0x0 |
|
| 8 |
XFFULL |
R |
0x0 |
External FIFO Full This bit provides information on the XFIFO when in the FIFO sub-mode of the Host Bus n mode with the XFFEN bit set in the EPIHBnCFG register.
The EPI0S26 signal reflects the status of this bit.
0x0 = The external device is not gating the clock.
0x1 = The XFIFO is signaling as full (the FIFO full signal is high).Attempts to write in this case are stalled until the XFIFO full signal goes low or the counter times out as specified by the MAXWAIT field.
|
| 7 |
XFEMPTY |
R |
0x0 |
External FIFO Empty This bit provides information on the XFIFO when in the FIFO sub-mode of the Host Bus n mode with the XFEEN bit set in the EPIHBnCFG register.
The EPI0S27 signal reflects the status of this bit.
0x0 = The external device is not gating the clock.
0x1 = The XFIFO is signaling as empty (the FIFO empty signal is high).Attempts to read in this case are stalled until the XFIFO empty signal goes low or the counter times out as specified by the MAXWAIT field.
|
| 6 |
INITSEQ |
R |
0x0 |
Initialization Sequence
0x0 = The SDRAM interface is not in the wakeup period.
0x1 = The SDRAM interface is running through the wakeup period (greater than 100 microseconds).If an attempt is made to read or write the SDRAM during this period, the access is held off until the wakeup period is complete.
|
| 5 |
WBUSY |
R |
0x0 |
Write Busy
0x0 = The external interface is not performing a write.
0x1 = The external interface is performing a write.
|
| 4 |
NBRBUSY |
R |
0x0 |
Non-Blocking Read Busy
0x0 = The external interface is not performing a non-blocking read.
0x1 = The external interface is performing a non-blocking read, or if the non-blocking read is paused due to a write.
|
| 3-1 |
RESERVED |
R |
0x0 |
|
| 0 |
ACTIVE |
R |
0x0 |
Register Active
0x0 = If NBRBUSY is set, the EPIRPSTD0 register is active.If the NBRBUSY bit is clear, then neither EPIRPSTDx register is active.
0x1 = The EPIRPSTD1 register is active.
|