SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 7-6 lists the memory-mapped registers for the FLASH. All register offset addresses not listed in Table 7-6 should be considered as reserved locations and the register contents should not be modified. Registers in this section are relative to the memory control base address of 0x400FD000.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | FMA | Flash Memory Address | Section 7.3.1 |
| 0x4 | FMD | Flash Memory Data | Section 7.3.2 |
| 0x8 | FMC | Flash Memory Control | Section 7.3.3 |
| 0xC | FCRIS | Flash Controller Raw Interrupt Status | Section 7.3.4 |
| 0x10 | FCIM | Flash Controller Interrupt Mask | Section 7.3.5 |
| 0x14 | FCMISC | Flash Controller Masked Interrupt Status and Clear | Section 7.3.6 |
| 0x20 | FMC2 | Flash Memory Control 2 | Section 7.3.7 |
| 0x30 | FWBVAL | Flash Write Buffer Valid | Section 7.3.8 |
| 0x3C | FLPEKEY | Flash Program/Erase Key | Section 7.3.9 |
| 0x100 to 0x17C | FWB0 to FWB31 | Flash Write Buffer 0 to Flash Write Buffer 32 | Section 7.3.10 |
| 0xFC0 | FLASHPP | Flash Peripheral Properties | Section 7.3.11 |
| 0xFC4 | SSIZE | SRAM Size | Section 7.3.12 |
| 0xFC8 | FLASHCONF | Flash Configuration Register | Section 7.3.13 |
| 0xFCC | ROMSWMAP | ROM Third-Party Software | Section 7.3.14 |
| 0xFD0 | FLASHDMASZ | Flash DMA Address Size | Section 7.3.15 |
| 0xFD4 | FLASHDMAST | Flash DMA Starting Address | Section 7.3.16 |
Complex bit access types are encoded to fit into small table cells. Table 7-7 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |