SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Figure 3-1 shows a high-level conceptual drawing of the JTAG module. The JTAG module is composed of the TAP controller and serial shift chains with parallel update registers. The TAP controller is a simple state machine controlled by the TCK and TMS inputs. The current state of the TAP controller depends on the sequence of values captured on TMS at the rising edge of TCK. The TAP controller determines when the serial shift chains capture new data, shift data from TDI toward TDO, and update the parallel load registers. The current state of the TAP controller also determines whether the IR chain or one of the DR chains is being accessed.
The serial shift chains with parallel load registers are comprised of one IR chain and multiple DR chains. The current instruction loaded in the parallel load register determines which DR chain is captured, shifted, or updated during the sequencing of the TAP controller.
Some instructions, like EXTEST, operate on data currently in a DR chain and do not capture, shift, or update any of the chains. Instructions that are not implemented decode to the BYPASS instruction to ensure that the serial path between TDI and TDO is always connected (see Table 3-2 for a list of implemented instructions).
Depending on the reset source, the effect on the JTAG module varies. The following reset sources reset the entire JTAG module:
The following reset sources reset only the JTAG pin configuration: