SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
GPIO Alternate Function Select (GPIOAFSEL)
NOTE
Tamper pins enabled in the Hibernate Tamper IO Control and Status (HIBTPIO) register override the AFSEL configuration.
The GPIOAFSEL register is the mode control select register. If a bit is clear, the pin is used as a GPIO and is controlled by the GPIO registers. Setting a bit in this register configures the corresponding GPIO line to be controlled by an associated peripheral. Several possible peripheral functions are multiplexed on each GPIO. The GPIO Port Control (GPIOPCTL) register is used to select one of the possible functions. See the device-specific data sheet for details on which functions are muxed on each GPIO pin. The reset value for this register is 0x00000000 for GPIO ports that are not listed in Table 17-16.
The table below shows special consideration GPIO pins. Most GPIO pins are configured as GPIOs and high-impedance by default (GPIOAFSEL = 0, GPIODEN = 0, GPIOPDR = 0, GPIOPUR = 0, and GPIOPCTL = 0). Special consideration pins may be programed to a nonGPIO function or may have special commit controls out of reset. In addition, a Power-On-Reset (POR) returns these GPIO to their original special consideration state.
| GPIO Pins | Default Reset State | GPIOAFSEL | GPIODEN | GPIOPDR | GPIOPUR | GPIOPCTL | GPIOCR |
|---|---|---|---|---|---|---|---|
| PC[3:0] | JTAG/SWD | 1 | 1 | 0 | 1 | 0x1 | 0 |
| PD[7] | GPIO(1) | 0 | 0 | 0 | 0 | 0x0 | 0 |
| PE[7] | GPIO(1) | 0 | 0 | 0 | 0 | 0x0 | 0 |
The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware signals including the GPIO pins that can function as JTAG/SWD signals and the NMI signal. The commit control process must be followed for these pins, even if they are programmed as alternate functions other than JTAG/SWD or NMI; see Section 17.3.4.
NOTE
If the device fails initialization during reset, the hardware toggles the TDO output as an indication of failure. Thus, during board layout, designers should not designate the TDO pin as a GPIO in sensitive applications where the possibility of toggling could affect the design.
NOTE
It is possible to create a software sequence that prevents the debugger from connecting to the MSP432E4 microcontroller. If the program code loaded into flash immediately changes the JTAG pins to their GPIO functionality, the debugger may not have enough time to connect and halt the controller before the JTAG pin functionality switches. As a result, the debugger may be locked out of the part. This issue can be avoided with a software routine that restores JTAG functionality based on an external or software trigger.
The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. Protection is provided for the GPIO pins that can be used as the four JTAG/SWD pins and the NMI pin (see for pin numbers). Writes to protected bits of the GPIO Alternate Function Select (GPIOAFSEL) register (see Section 17.5.10), GPIO Pullup Select (GPIOPUR) register (seeSection 17.5.15), GPIO Pulldown Select (GPIOPDR) register (see Section 17.5.16), and GPIO Digital Enable (GPIODEN) register (see Section 17.5.18) are not committed to storage unless the GPIO Lock (GPIOLOCK) register (seeSection 17.5.19) has been unlocked and the appropriate bits of the GPIO Commit (GPIOCR) register (see Section 17.5.20) have been set.
When using the I2C module, in addition to setting the GPIOAFSEL register bits for the I2C clock and data pins, the data pins should be set to open drain using the GPIO Open Drain Select (GPIOODR) register (see examples in Section 17.4).
GPIOAFSEL is shown in Figure 17-14 and described in Table 17-17.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | AFSEL | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-X | ||||||||||||||||||||||||||||||