SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
NOTE
The GPIO registers in this chapter are duplicated in each GPIO block; however, depending on the block, all eight bits may not be connected to a GPIO pad. In those cases, writing to unconnected bits has no effect, and reading unconnected bits returns no meaningful data. See the device-specific data sheet for the GPIOs included on any given device.
The offset is a hexadecimal increment to the register's address, relative to the base address of that GPIO port:
Note that each GPIO module clock must be enabled before the registers can be programmed (see Section 4.2.87). There must be a delay of 3 system clocks after the GPIO module clock is enabled before any GPIO module registers are accessed.
The table below shows special consideration GPIO pins. Most GPIO pins are configured as GPIOs and high-impedance by default (GPIOAFSEL = 0, GPIODEN = 0, GPIOPDR = 0, GPIOPUR = 0, and GPIOPCTL = 0). Special consideration pins may be programed to a nonGPIO function or may have special commit controls out of reset. In addition, a Power-On-Reset (POR) returns these GPIO to their original special consideration state.
| GPIO Pins | Default Reset State | GPIOAFSEL | GPIODEN | GPIOPDR | GPIOPUR | GPIOPCTL | GPIOCR |
|---|---|---|---|---|---|---|---|
| PC[3:0] | JTAG/SWD | 1 | 1 | 0 | 1 | 0x1 | 0 |
| PD[7] | GPIO(1) | 0 | 0 | 0 | 0 | 0x0 | 0 |
| PE[7] | GPIO(1) | 0 | 0 | 0 | 0 | 0x0 | 0 |
The GPIO commit control registers provide a layer of protection against accidental programming of critical hardware signals including the GPIO pins that can function as JTAG/SWD signals and the NMI signal. The commit control process must be followed for these pins, even if they are programmed as alternate functions other than JTAG/SWD or NMI; see Section 17.3.4.
NOTE
If the device fails initialization during reset, the hardware toggles the TDO output as an indication of failure. Thus, during board layout, designers should not designate the TDO pin as a GPIO in sensitive applications where the possibility of toggling could affect the design.
The default register type for the GPIOCR register is read-only for all GPIO pins with the exception of the NMI pin and the four JTAG/SWD pins (see the device-specific data sheet for pin numbers). These six pins are the only GPIOs that are protected by the GPIOCR register. Because of this, the register type for the corresponding GPIO Ports is RW.
The default reset value for the GPIOCR register is 0x000000FF for all GPIO pins, with the exception of the NMI and JTAG/SWD pins (see the device-specific data sheet for pin numbers). To ensure that the JTAG and NMI pins are not accidentally programmed as GPIO pins, these pins default to noncommittable. Because of this, the default reset value of GPIOCR changes for the corresponding ports.
Table 17-5 lists the memory-mapped registers for the GPIO. All register offset addresses not listed in Table 17-5 should be considered as reserved locations and the register contents should not be modified.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | GPIODATA | GPIO Data | Section 17.5.1 |
| 0x400 | GPIODIR | GPIO Direction | Section 17.5.2 |
| 0x404 | GPIOIS | GPIO Interrupt Sense | Section 17.5.3 |
| 0x408 | GPIOIBE | GPIO Interrupt Both Edges | Section 17.5.4 |
| 0x40C | GPIOIEV | GPIO Interrupt Event | Section 17.5.5 |
| 0x410 | GPIOIM | GPIO Interrupt Mask | Section 17.5.6 |
| 0x414 | GPIORIS | GPIO Raw Interrupt Status | Section 17.5.7 |
| 0x418 | GPIOMIS | GPIO Masked Interrupt Status | Section 17.5.8 |
| 0x41C | GPIOICR | GPIO Interrupt Clear | Section 17.5.9 |
| 0x420 | GPIOAFSEL | GPIO Alternate Function Select | Section 17.5.10 |
| 0x500 | GPIODR2R | GPIO 2-mA Drive Select | Section 17.5.11 |
| 0x504 | GPIODR4R | GPIO 4-mA Drive Select | Section 17.5.12 |
| 0x508 | GPIODR8R | GPIO 8-mA Drive Select | Section 17.5.13 |
| 0x50C | GPIOODR | GPIO Open Drain Select | Section 17.5.14 |
| 0x510 | GPIOPUR | GPIO Pullup Select | Section 17.5.15 |
| 0x514 | GPIOPDR | GPIO Pulldown Select | Section 17.5.16 |
| 0x518 | GPIOSLR | GPIO Slew Rate Control Select | Section 17.5.17 |
| 0x51C | GPIODEN | GPIO Digital Enable | Section 17.5.18 |
| 0x520 | GPIOLOCK | GPIO Lock | Section 17.5.19 |
| 0x524 | GPIOCR | GPIO Commit | Section 17.5.20 |
| 0x528 | GPIOAMSEL | GPIO Analog Mode Select | Section 17.5.21 |
| 0x52C | GPIOPCTL | GPIO Port Control | Section 17.5.22 |
| 0x530 | GPIOADCCTL | GPIO ADC Control | Section 17.5.23 |
| 0x534 | GPIODMACTL | GPIO DMA Control | Section 17.5.24 |
| 0x538 | GPIOSI | GPIO Select Interrupt | Section 17.5.25 |
| 0x53C | GPIODR12R | GPIO 12-mA Drive Select | Section 17.5.26 |
| 0x540 | GPIOWAKEPEN | GPIO Wake Pin Enable | Section 17.5.27 |
| 0x544 | GPIOWAKELVL | GPIO Wake Level | Section 17.5.28 |
| 0x548 | GPIOWAKESTAT | GPIO Wake Status | Section 17.5.29 |
| 0xFC0 | GPIOPP | GPIO Peripheral Property | Section 17.5.30 |
| 0xFC4 | GPIOPC | GPIO Peripheral Configuration | Section 17.5.31 |
| 0xFD0 | GPIOPeriphID4 | GPIO Peripheral Identification 4 | Section 17.5.32 |
| 0xFD4 | GPIOPeriphID5 | GPIO Peripheral Identification 5 | Section 17.5.33 |
| 0xFD8 | GPIOPeriphID6 | GPIO Peripheral Identification 6 | Section 17.5.34 |
| 0xFDC | GPIOPeriphID7 | GPIO Peripheral Identification 7 | Section 17.5.35 |
| 0xFE0 | GPIOPeriphID0 | GPIO Peripheral Identification 0 | Section 17.5.36 |
| 0xFE4 | GPIOPeriphID1 | GPIO Peripheral Identification 1 | Section 17.5.37 |
| 0xFE8 | GPIOPeriphID2 | GPIO Peripheral Identification 2 | Section 17.5.38 |
| 0xFEC | GPIOPeriphID3 | GPIO Peripheral Identification 3 | Section 17.5.39 |
| 0xFF0 | GPIOPCellID0 | GPIO PrimeCell Identification 0 | Section 17.5.40 |
| 0xFF4 | GPIOPCellID1 | GPIO PrimeCell Identification 1 | Section 17.5.41 |
| 0xFF8 | GPIOPCellID2 | GPIO PrimeCell Identification 2 | Section 17.5.42 |
| 0xFFC | GPIOPCellID3 | GPIO PrimeCell Identification 3 | Section 17.5.43 |
Complex bit access types are encoded to fit into small table cells. Table 17-6 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |