SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
GPIO Raw Interrupt Status (GPIORIS)
The GPIORIS register is the raw interrupt status register. A bit in this register is set when an interrupt condition occurs on the corresponding GPIO pin or if a µDMA done interrupt occurs. If the corresponding bit in the GPIO Interrupt Mask (GPIOIM) register (see Section 17.5.6) is set, the interrupt is sent to the interrupt controller. Bits read as zero indicate that corresponding input pins have not initiated an interrupt. For a GPIO level-detect interrupt, the interrupt signal generating the interrupt must be held until serviced. Once the input signal deasserts from the interrupt generating logical sense, the corresponding RIS bit in the GPIORIS register clears. For a GPIO edge-detect interrupt, the RIS bit in the GPIORIS register is cleared by writing a 1 to the corresponding bit in the GPIO Interrupt Clear (GPIOICR) register. The corresponding GPIOMIS bit reflects the masked value of the RIS bit.
GPIORIS is shown in Figure 17-11 and described in Table 17-13.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | DMARIS | ||||||
| R-0x0 | R-0x0 | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RIS | |||||||
| R-0x0 | |||||||