SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
GPIO 2-mA Drive Select (GPIODR2R)
The GPIODR2R register is the 2-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and DRV8 bit in the GPIODR8R register are automatically cleared by hardware. By default, all GPIO pins have 2-mA drive.
NOTE
GPIODR2R is shown in Figure 17-15 and described in Table 17-18.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DRV2 | ||||||||||||||||||||||||||||||
R-0x0 | R/W-0xFF | ||||||||||||||||||||||||||||||