17.5.25 GPIOSI Register (Offset = 0x538) [reset = 0x0]
GPIO Select Interrupt (GPIOSI)
This register is used to enable individual interrupts for each pin.
NOTE
This register is only available on Port P and Port Q.
GPIOSI is shown in Figure 17-29 and described in Table 17-36.
Return to Summary Table.
Figure 17-29 GPIOSI Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
SUM |
| R-0x0 |
R/W-0x0 |
|
Table 17-36 GPIOSI Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-1 |
RESERVED |
R |
0x0 |
|
| 0 |
SUM |
R/W |
0x0 |
Summary Interrupt.
0x0 = All port pin interrupts are ORed together to produce a summary interrupt. The ORed summary interrupt occurs on bit 0 of the GPIORIS register. For summary interrupt mode, software should set the GPIOIM register to 0xFF and mask the port pin interrupts 1 through 7 in the Interrupt Clear Enable (DISn) register. When servicing this interrupt, write a 1 to the corresponding bit in the UNPENDn register to clear the pending interrupt in the NVIC and clear the GPIORIS register pin interrupt bits by setting the IC field of the GPIOICR register to 0xFF.
0x1 = Each pin has its own interrupt vector.
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