SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
GPIO Interrupt Mask (GPIOIM)
The GPIOIM register is the interrupt mask register. Setting a bit in the GPIOIM register allows interrupts that are generated by the corresponding pin to be sent to the interrupt controller on the combined interrupt signal. Clearing a bit prevents an interrupt on the corresponding pin from being sent to the interrupt controller. All bits are cleared by a reset.
GPIOIM is shown in Figure 17-10 and described in Table 17-12.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAIME | ||||||
R-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
IME | |||||||
R/W-0x0 | |||||||