SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
GPIO Masked Interrupt Status (GPIOMIS)
The GPIOMIS register is the masked interrupt status register. If a bit is set in this register, the corresponding interrupt has triggered an interrupt to the interrupt controller. If a bit is clear, either no interrupt has been generated, or the interrupt is masked.
Note that if the Port B GPIOADCCTL register is cleared, PB4 can still be used as an external trigger for the ADC. This is a legacy mode which allows code written for previous devices to operate on this microcontroller.
GPIOMIS is the state of the interrupt after masking.
GPIOMIS is shown in Figure 17-12 and described in Table 17-14.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | DMAMIS | ||||||
R-0x0 | R-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MIS | |||||||
R-0x0 | |||||||