17.5.31 GPIOPC Register (Offset = 0xFC4) [reset = 0x0]
GPIO Peripheral Configuration (GPIOPC)
This GPIOPC register controls the extended drive modes of the GPIO and must be configured before the GPIODRnR registers in order for extended drive mode to take effect. When the EDE bit in GPIOPP register is set and the EDMn bit field is nonzero, the GPIODRnR registers do not drive their default value, but instead output an incremental drive strength, which has an additive effect. This allows for more drive strength possibilities. When the EDE bit is set and the EDMn bit field is nonzero, the 2 mA driver is always enabled. Any bits enabled in the GPIODR4R register will add an additional 2 mA; any bits set in the GPIODR8R add an extra 4 mA of drive. The GPIODR12R register is only valid when the EDMn value is 0x3. For this encoding, setting a bit in the GPIODR12R register adds 4 mA of drive to the already existing 8 mA, for a 12 mA drive strength. Table 17-1 shows the drive capability options. If EDMn is 0x00, then the GPIODR2R, GPIODR4R, and GPIODR8R function as stated in their default register description.
Table 17-42 GPIO Drive Strength Options
| EDE (GPIOPP) |
EDMn (GPIOPC) |
GPIODR12R (+4 mA) |
GPIODR8R (+4 mA) |
GPIODR4R (+2 mA) |
GPIODR2R (2 mA) |
Drive (mA) |
| X |
0x0 |
N/A |
0 |
0 |
1 |
2 |
| 0 |
1 |
0 |
4 |
| 1 |
0 |
0 |
8 |
| 1 |
0x1 |
N/A |
0 |
0 |
N/A |
2 |
| 0 |
1 |
N/A |
4 |
| 1 |
0 |
N/A |
6 |
| 1 |
1 |
N/A |
8 |
| 1 |
0x3 |
0 |
0 |
0 |
N/A |
2 |
| 0 |
0 |
1 |
N/A |
4 |
| 0 |
1 |
0 |
N/A |
6 |
| 0 |
1 |
1 |
N/A |
8 |
| 1 |
1 |
0 |
N/A |
10 |
| 1 |
1 |
1 |
N/A |
12 |
| 1 |
0 |
N/A |
N/A |
N/A |
| 1 |
0x2 |
N/A |
N/A |
N/A |
N/A |
N/A |
GPIOPC is shown in Figure 17-35 and described in Table 17-43.
Return to Summary Table.
Figure 17-35 GPIOPC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| EDM7 |
EDM6 |
EDM5 |
EDM4 |
EDM3 |
EDM2 |
EDM1 |
EDM0 |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 17-43 GPIOPC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-16 |
RESERVED |
R |
0x0 |
|
| 15-14 |
EDM7 |
R/W |
0x0 |
Extended Drive Mode Bit 7.
Same encoding as EDM0, but applies to bit 7 of GPIO port. |
| 13-12 |
EDM6 |
R/W |
0x0 |
Extended Drive Mode Bit 6.
Same encoding as EDM0, but applies to bit 6 of GPIO port. |
| 11-10 |
EDM5 |
R/W |
0x0 |
Extended Drive Mode Bit 5.
Same encoding as EDM0, but applies to bit 5 of GPIO port. |
| 9-8 |
EDM4 |
R/W |
0x0 |
Extended Drive Mode Bit 4.
Same encoding as EDM0, but applies to bit 4 of GPIO port. |
| 7-6 |
EDM3 |
R/W |
0x0 |
Extended Drive Mode Bit 3.
Same encoding as EDM0, but applies to bit 3 of GPIO port. |
| 5-4 |
EDM2 |
R/W |
0x0 |
Extended Drive Mode Bit 2.
Same encoding as EDM0, but applies to bit 2 of GPIO port. |
| 3-2 |
EDM1 |
R/W |
0x0 |
Extended Drive Mode Bit 1.
Same encoding as EDM0, but applies to bit 1 of GPIO port. |
| 1-0 |
EDM0 |
R/W |
0x0 |
Extended Drive Mode Bit 0.
This field controls extended drive modes of bit 0 of the GPIO port.
Note that depending on the encoding used the GPIO drive strength control registers may change their decoding.
Moreover, the write one, clear other register behavior may be disabled.
0x0 = Drive values of 2, 4 and 8 mA are maintained. GPIO n Drive Select (GPIODRnR) registers function as normal.
0x1 = An additional 6 mA option is provided.Write one, clear other behavior of GPIODDRnR registers is disabled. A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R register bit adds an additional 4 mA.
0x2 = reserved
0x3 = Additional drive strength options of 6, 10, and 12 mA are provided. The write one, clear other behavior of GPIODDRnR registers is disabled. A 2 mA driver is always enabled; setting the corresponding GPIODR4R register bit adds 2 mA and setting the corresponding GPIODR8R of GPIODR12R register bit adds an additional 4 mA.
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