4.2.6 MISC Register (Offset = 0x58) [reset = 0x0]
Masked Interrupt Status and Clear (MISC)
On a read, this register gives the current masked status value of the corresponding interrupt in the Raw Interrupt Status (RIS) register. All of the bits are RW1C, thus writing 1 to a bit clears the corresponding raw interrupt bit in the RIS register (see Section 4.2.4).
MISC is shown in Figure 4-12 and described in Table 4-16.
Return to Summary Table.
Figure 4-12 MISC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
MOSCPUPMIS |
| R-0x0 |
R/W1C-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
PLLLMIS |
RESERVED |
MOFMIS |
RESERVED |
BORMIS |
RESERVED |
| R-0x0 |
R/W1C-0x0 |
R-0x0 |
R/W1C-0x0 |
R-0x0 |
R/W1C-0x0 |
R-0x0 |
|
Table 4-16 MISC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-9 |
RESERVED |
R |
0x0 |
|
| 8 |
MOSCPUPMIS |
R/W1C |
0x0 |
MOSC Power Up Masked Interrupt Status
0x0 = When read, 0 indicates that sufficient time has not passed for the MOSC PLL to lock. Writing 0 has no effect on the state of this bit.
0x1 = When read, 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the MOSC PLL to lock. Writing 1 to this bit clears it and also the MOSCPUPRIS bit in the RIS register.
|
| 7 |
RESERVED |
R |
0x0 |
|
| 6 |
PLLLMIS |
R/W1C |
0x0 |
PLL Lock Masked Interrupt Status
0x0 = When read, 0 indicates that sufficient time has not passed for the PLL to lock. Writing 0 has no effect on the state of this bit.
0x1 = When read, 1 indicates that an unmasked interrupt was signaled because sufficient time has passed for the PLL to lock. Writing 1 to this bit clears it and also the PLLLRIS bit in the RIS register.
|
| 5-4 |
RESERVED |
R |
0x0 |
|
| 3 |
MOFMIS |
R/W1C |
0x0 |
Main Oscillator Failure Masked Interrupt Status
0x0 = When read, 0 indicates that the main oscillator has not failed. Writing 0 has no effect on the state of this bit.
0x1 = When read, 1 indicates that an unmasked interrupt was signaled because the main oscillator failed. Writing 1 to this bit clears it and also the MOFRIS bit in the RIS register.
|
| 2 |
RESERVED |
R |
0x0 |
|
| 1 |
BORMIS |
R/W1C |
0x0 |
BOR Masked Interrupt Status
0x0 = When read, 0 indicates that a brownout condition has not occurred. Writing 0 has no effect on the state of this bit.
0x1 = When read, 1 indicates that an unmasked interrupt was signaled because of a brownout condition. Writing 1 to this bit clears it and also the BORRIS bit in the RIS register.
|
| 0 |
RESERVED |
R |
0x0 |
|