SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PSR is shown in Figure 1-8 and described in Table 1-9.
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NOTE
This register is also referred to as xPSR.
The Program Status Register (PSR) has three functions, and the register bits are assigned to the different functions:
The PSR, IPSR, and EPSR registers can only be accessed in privileged mode; the APSR register can be accessed in either privileged or unprivileged mode.
APSR contains the current state of the condition flags from previous instruction executions.
EPSR contains the Thumb state bit and the execution state bits for the If-Then (IT) instruction or the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction. Attempts to read the EPSR directly through application software using the MSR instruction always return zero. Attempts to write the EPSR using the MSR instruction in application software are always ignored. Fault handlers can examine the EPSR value in the stacked PSR to determine the operation that faulted (see Section 1.6.7).
IPSR contains the exception type number of the current Interrupt Service Routine (ISR).
These registers can be accessed individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example, all of the registers can be read using PSR with the MRS instruction, or APSR only can be written to using APSR with the MSR instruction. Table 1-8 lists the possible register combinations for the PSR. See the MRS and MSR instruction descriptions in the Cortex-M4 instruction set chapter in the Arm® Cortex-M4 Devices Generic User Guide for more information about how to access the program status registers.
| Register | Type | Combination |
|---|---|---|
| PSR | RW(1)(2) | APSR, EPSR, and IPSR |
| IEPSR | RO | EPSR and IPSR |
| IAPSR | RW(1) | APSR and IPSR |
| EAPSR | RW(2) | APSR and EPSR |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| N | Z | C | V | Q | ICI / IT | THUMB | |
| R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R-0h | R-1h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | GE | ||||||
| R-0h | R/W-0h | ||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ICI / IT | RESERVED | ||||||
| R-0h | R-0h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ISRNUM | |||||||
| R-0h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31 | N | R/W | 0h |
APSR Negative or Less Flag |
| 30 | Z | R/W | 0h |
APSR Zero Flag. The value of this bit is only meaningful when accessing PSR or APSR. |
| 29 | C | R/W | 0h |
APSR Carry or Borrow Flag. The value of this bit is only meaningful when accessing PSR or APSR. |
| 28 | V | R/W | 0h |
APSR Overflow Flag. The value of this bit is only meaningful when accessing PSR or APSR. |
| 27 | Q | R/W | 0h |
APSR DSP Overflow and Saturation Flag. The value of this bit is only meaningful when accessing PSR or APSR. This bit is cleared by software using an MRS instruction. |
| 26:25 | ICI / IT | R | 0h |
EPSR ICI / IT status. These bits, along with bits 15-10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26-25 are zero. The If-Then block contains up to four instructions following an IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex-M4 instruction set chapter in the Arm Cortex-M4 Devices Generic User Guide for more information. The value of this field is only meaningful when accessing PSR or EPSR. These EPSR bits cannot be accessed using MRS and MSR instructions, but the definitions are provided to allow the stacked (E)PSR value to be decoded within an exception handler. |
| 24 | THUMB | R | 1h |
EPSR Thumb State. This bit indicates the Thumb state and should always be set. The following can clear the THUMB bit:
Attempting to execute instructions when this bit is clear results in a fault or lockup. See the Lockup section for more information. The value of this bit is only meaningful when accessing PSR or EPSR. |
| 23:20 | RESERVED | R | 0h |
|
| 19:16 | GE | R/W | 0h |
Greater Than or Equal Flags. See the description of the SEL instruction in the Cortex-M4 instruction set chapter in the Arm Cortex-M4 Devices Generic User Guide for more information. The value of this field is only meaningful when accessing PSR or APSR. |
| 15:10 | ICI / IT | R | 0h |
EPSR ICI / IT status. These bits, along with bits 26-25, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When an interrupt occurs during the execution of an LDM, STM, PUSH POP, VLDM, VSTM, VPUSH, or VPOP instruction, the processor stops the load multiple or store multiple instruction operation temporarily and stores the next register operand in the multiple operation to bits 15-12. After servicing the interrupt, the processor returns to the register pointed to by bits 15-12 and resumes execution of the multiple load or store instruction. When EPSR holds the ICI execution state, bits 11-10 are zero. The If-Then block contains up to four instructions following a 16-bit IT instruction. Each instruction in the block is conditional. The conditions for the instructions are either all the same, or some can be the inverse of others. See the Cortex-M4 instruction set chapter in the Arm Cortex-M4 Devices Generic User Guide for more information. The value of this field is only meaningful when accessing PSR or EPSR. |
| 9:8 | RESERVED | R | 0h |
|
| 7:0 | ISRNUM | R | 0h |
IPSR ISR Number. This field contains the exception type number of the current Interrupt Service Routine (ISR). The value of this field is only meaningful when accessing PSR or IPSR. 00h = Thread mode 01h = Reserved 02h = NMI 03h = Hard fault 04h = Memory management fault 05h = Bus fault 06h = Usage fault 07h-0Ah = Reserved 0Bh = SVCall 0Ch = Reserved for Debug 0Dh = Reserved 0Eh = PendSV 0Fh = SysTick 10h = Interrupt Vector 0 11h = Interrupt Vector 1 ... ... 81h = Interrupt Vector 113 |