21.5.32 PWMCC Register (Offset = 0xFC8) [reset = 0x5]
PWM Clock Configuration (PWMCC), offset 0xFC8
The PWMCC register controls the clock source for the PWM module.
PWMCC is shown in Figure 21-38 and described in Table 21-34.
Return to Summary Table.
Figure 21-38 PWMCC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
USEPWM |
| R-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| reserved_2 |
PWMDIV |
| R-0x0 |
R/W-0x5 |
|
Table 21-34 PWMCC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-9 |
RESERVED |
R |
0x0 |
|
| 8 |
USEPWM |
R/W |
0x0 |
Use PWM Clock Divisor.
0x0 = The system clock is the source of PWM unit clock.
0x1 = The PWM clock divider is the source of PWM unit clock.
|
| 7-3 |
RESERVED |
R |
0x0 |
|
| 2-0 |
PWMDIV |
R/W |
0x5 |
PWM Clock Divider. This field specifies the PWM clock frequency as a division of the system clock.
0x0 = /2
0x1 = /4
0x2 = /8
0x3 = /16
0x4 = /32
0x5 = /64
0x6 = Reserved
0x7 = Reserved
|