SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 21-1 lists the memory-mapped registers for the PWM. All register offset addresses not listed in Table 21-1 should be considered as reserved locations and the register contents should not be modified.
The offsets are relative to the base address of the PWM module: 0x40028000.
The PWM module clock must be enabled before the registers can be programmed. There must be a delay of 3 system clock cycles after the PWM module clock is enabled before any PWM module registers are accessed.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | PWMCTL | PWM Master Control | Section 21.5.1 |
| 0x4 | PWMSYNC | PWM Time Base Sync | Section 21.5.2 |
| 0x8 | PWMENABLE | PWM Output Enable | Section 21.5.3 |
| 0xC | PWMINVERT | PWM Output Inversion | Section 21.5.4 |
| 0x10 | PWMFAULT | PWM Output Fault | Section 21.5.5 |
| 0x14 | PWMINTEN | PWM Interrupt Enable | Section 21.5.6 |
| 0x18 | PWMRIS | PWM Raw Interrupt Status | Section 21.5.7 |
| 0x1C | PWMISC | PWM Interrupt Status and Clear | Section 21.5.8 |
| 0x20 | PWMSTATUS | PWM Status | Section 21.5.9 |
| 0x24 | PWMFAULTVAL | PWM Fault Condition Value | Section 21.5.10 |
| 0x28 | PWMENUPD | PWM Enable Update | Section 21.5.11 |
| 0x40 | PWM0CTL | PWM0 Control | Section 21.5.12 |
| 0x44 | PWM0INTEN | PWM0 Interrupt and Trigger Enable | Section 21.5.13 |
| 0x48 | PWM0RIS | PWM0 Raw Interrupt Status | Section 21.5.14 |
| 0x4C | PWM0ISC | PWM0 Interrupt Status and Clear | Section 21.5.15 |
| 0x50 | PWM0LOAD | PWM0 Load | Section 21.5.16 |
| 0x54 | PWM0COUNT | PWM0 Counter | Section 21.5.17 |
| 0x58 | PWM0CMPA | PWM0 Compare A | Section 21.5.18 |
| 0x5C | PWM0CMPB | PWM0 Compare B | Section 21.5.19 |
| 0x60 | PWM0GENA | PWM0 Generator A Control | Section 21.5.20 |
| 0x64 | PWM0GENB | PWM0 Generator B Control | Section 21.5.21 |
| 0x68 | PWM0DBCTL | PWM0 Dead-Band Control | Section 21.5.22 |
| 0x6C | PWM0DBRISE | PWM0 Dead-Band Rising-Edge Delay | Section 21.5.23 |
| 0x70 | PWM0DBFALL | PWM0 Dead-Band Falling-Edge-Delay | Section 21.5.24 |
| 0x74 | PWM0FLTSRC0 | PWM0 Fault Source 0 | Section 21.5.25 |
| 0x78 | PWM0FLTSRC1 | PWM0 Fault Source 1 | Section 21.5.26 |
| 0x7C | PWM0MINFLTPER | PWM0 Minimum Fault Period | Section 21.5.27 |
| 0x080 | PWM1CTL | PWM1 Control | Section 21.5.12 |
| 0x084 | PWM1INTEN | PWM1 Interrupt and Trigger Enable | Section 21.5.13 |
| 0x088 | PWM1RIS | PWM1 Raw Interrupt Status | Section 21.5.14 |
| 0x08C | PWM1ISC | PWM1 Interrupt Status and Clear | Section 21.5.15 |
| 0x090 | PWM1LOAD | PWM1 Load | Section 21.5.16 |
| 0x094 | PWM1COUNT | PWM1 Counter | Section 21.5.17 |
| 0x098 | PWM1CMPA | PWM1 Compare A | Section 21.5.18 |
| 0x09C | PWM1CMPB | PWM1 Compare B | Section 21.5.19 |
| 0x0A0 | PWM1GENA | PWM1 Generator A Control | Section 21.5.20 |
| 0x0A4 | PWM1GENB | PWM1 Generator B Control | Section 21.5.21 |
| 0x0A8 | PWM1DBCTL | PWM1 Dead-Band Control | Section 21.5.22 |
| 0x0AC | PWM1DBRISE | PWM1 Dead-Band Rising-Edge Delay | Section 21.5.23 |
| 0x0B0 | PWM1DBFALL | PWM1 Dead-Band Falling-Edge-Delay | Section 21.5.24 |
| 0x0B4 | PWM1FLTSRC0 | PWM1 Fault Source 0 | Section 21.5.25 |
| 0x0B8 | PWM1FLTSRC1 | PWM1 Fault Source 1 | Section 21.5.26 |
| 0x0BC | PWM1MINFLTPER | PWM1 Minimum Fault Period | Section 21.5.27 |
| 0x0C0 | PWM2CTL | PWM2 Control | Section 21.5.12 |
| 0x0C4 | PWM2INTEN | PWM2 Interrupt and Trigger Enable | Section 21.5.13 |
| 0x0C8 | PWM2RIS | PWM2 Raw Interrupt Status | Section 21.5.14 |
| 0x0CC | PWM2ISC | PWM2 Interrupt Status and Clear | Section 21.5.15 |
| 0x0D0 | PWM2LOAD | PWM2 Load | Section 21.5.16 |
| 0x0D4 | PWM2COUNT | PWM2 Counter | Section 21.5.17 |
| 0x0D8 | PWM2CMPA | PWM2 Compare A | Section 21.5.18 |
| 0x0DC | PWM2CMPB | PWM2 Compare B | Section 21.5.19 |
| 0x0E0 | PWM2GENA | PWM2 Generator A Control | Section 21.5.20 |
| 0x0E4 | PWM2GENB | PWM2 Generator B Control | Section 21.5.21 |
| 0x0E8 | PWM2DBCTL | PWM2 Dead-Band Control | Section 21.5.22 |
| 0x0EC | PWM2DBRISE | PWM2 Dead-Band Rising-Edge Delay | Section 21.5.23 |
| 0x0F0 | PWM2DBFALL | PWM2 Dead-Band Falling-Edge-Delay | Section 21.5.24 |
| 0x0F4 | PWM2FLTSRC0 | PWM2 Fault Source 0 | Section 21.5.25 |
| 0x0F8 | PWM2FLTSRC1 | PWM2 Fault Source 1 | Section 21.5.26 |
| 0x0FC | PWM2MINFLTPER | PWM2 Minimum Fault Period | Section 21.5.27 |
| 0x100 | PWM3CTL | PWM3 Control | Section 21.5.12 |
| 0x104 | PWM3INTEN | PWM3 Interrupt and Trigger Enable | Section 21.5.13 |
| 0x108 | PWM3RIS | PWM3 Raw Interrupt Status | Section 21.5.14 |
| 0x10C | PWM3ISC | PWM3 Interrupt Status and Clear | Section 21.5.15 |
| 0x110 | PWM3LOAD | PWM3 Load | Section 21.5.16 |
| 0x114 | PWM3COUNT | PWM3 Counter | Section 21.5.17 |
| 0x118 | PWM3CMPA | PWM3 Compare A | Section 21.5.18 |
| 0x11C | PWM3CMPB | PWM3 Compare B | Section 21.5.19 |
| 0x120 | PWM3GENA | PWM3 Generator A Control | Section 21.5.20 |
| 0x124 | PWM3GENB | PWM3 Generator B Control | Section 21.5.21 |
| 0x128 | PWM3DBCTL | PWM3 Dead-Band Control | Section 21.5.22 |
| 0x12C | PWM3DBRISE | PWM3 Dead-Band Rising-Edge Delay | Section 21.5.23 |
| 0x130 | PWM3DBFALL | PWM3 Dead-Band Falling-Edge-Delay | Section 21.5.24 |
| 0x134 | PWM3FLTSRC0 | PWM3 Fault Source 0 | Section 21.5.25 |
| 0x138 | PWM3FLTSRC1 | PWM3 Fault Source 1 | Section 21.5.26 |
| 0x13C | PWM3MINFLTPER | PWM3 Minimum Fault Period | Section 21.5.27 |
| 0x800 | PWM0FLTSEN | PWM0 Fault Pin Logic Sense | Section 21.5.28 |
| 0x804 | PWM0FLTSTAT0 | PWM0 Fault Status 0 | Section 21.5.29 |
| 0x808 | PWM0FLTSTAT1 | PWM0 Fault Status 1 | Section 21.5.30 |
| 0x880 | PWM1FLTSEN | PWM1 Fault Pin Logic Sense | Section 21.5.28 |
| 0x884 | PWM1FLTSTAT0 | PWM1 Fault Status 0 | Section 21.5.29 |
| 0x888 | PWM1FLTSTAT1 | PWM1 Fault Status 1 | Section 21.5.30 |
| 0x900 | PWM2FLTSEN | PWM2 Fault Pin Logic Sense | Section 21.5.28 |
| 0x904 | PWM2FLTSTAT0 | PWM2 Fault Status 0 | Section 21.5.29 |
| 0x908 | PWM2FLTSTAT1 | PWM2 Fault Status 1 | Section 21.5.30 |
| 0x980 | PWM3FLTSEN | PWM3 Fault Pin Logic Sense | Section 21.5.28 |
| 0x984 | PWM3FLTSTAT0 | PWM3 Fault Status 0 | Section 21.5.29 |
| 0x988 | PWM3FLTSTAT1 | PWM3 Fault Status 1 | Section 21.5.30 |
| 0xFC0 | PWMPP | PWM Peripheral Properties | Section 21.5.31 |
| 0xFC8 | PWMCC | PWM Clock Configuration | Section 21.5.32 |
Complex bit access types are encoded to fit into small table cells. Table 21-2 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |