21.5.30 PWMnFLTSTAT1 Register [reset = 0x0]
PWM0 Fault Status 1 (PWM0FLTSTAT1), offset 0x808
PWM1 Fault Status 1 (PWM1FLTSTAT1), offset 0x888
PWM2 Fault Status 1 (PWM2FLTSTAT1), offset 0x908
PWM3 Fault Status 1 (PWM3FLTSTAT1), offset 0x988
Along with the PWMnFLTSTAT0 register, this register provides status regarding the fault condition inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT1 register are read-only (R) and provide the current state of the digital comparator triggers.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT1 register are read / write 1 to clear (RW1C) and provide a latched version of the digital comparator triggers. In this mode, the register bits are cleared by writing a 1 to a set bit. The contents of this register can only be written if the fault source extensions are enabled (the FLTSRC bit in the PWMnCTL register is set).
NOTE
The fault status registers, PWMnFLTSTAT0 and PWMnFLTSTAT1, reflect the status of all fault sources, regardless of what fault sources are enabled for that particular generator.
PWMnFLTSTAT1 is shown in Figure 21-36 and described in Table 21-32.
Return to Summary Table.
Figure 21-36 PWMnFLTSTAT1 Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| DCMP7 |
DCMP6 |
DCMP5 |
DCMP4 |
DCMP3 |
DCMP2 |
DCMP1 |
DCMP0 |
| 0x0 |
0x0 |
0x0 |
0x0 |
0x0 |
0x0 |
0x0 |
0x0 |
|
Table 21-32 PWMnFLTSTAT1 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0x0 |
|
| 7 |
DCMP7 |
|
0x0 |
Digital Comparator 7 Trigger.
If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 7 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger.
- If DCMP7 is set, the trigger transitioned to the active state previously.
- If DCMP7 is clear, the trigger has not transitioned to the active state since the last time it was cleared.
- The DCMP7 bit is cleared by writing it with the value 1.
|
| 6 |
DCMP6 |
|
0x0 |
Digital Comparator 6 Trigger.
If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 6 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger.
- If DCMP6 is set, the trigger transitioned to the active state previously.
- If DCMP6 is clear, the trigger has not transitioned to the active state since the last time it was cleared.
- The DCMP6 bit is cleared by writing it with the value 1.
|
| 5 |
DCMP5 |
|
0x0 |
Digital Comparator 5 Trigger.
If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 5 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger.
- If DCMP5 is set, the trigger transitioned to the active state previously.
- If DCMP5 is clear, the trigger has not transitioned to the active state since the last time it was cleared.
- The DCMP5 bit is cleared by writing it with the value 1.
|
| 4 |
DCMP4 |
|
0x0 |
Digital Comparator 4 Trigger.
If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 4 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger.
- If DCMP4 is set, the trigger transitioned to the active state previously.
- If DCMP4 is clear, the trigger has not transitioned to the active state since the last time it was cleared.
- The DCMP4 bit is cleared by writing it with the value 1.
|
| 3 |
DCMP3 |
|
0x0 |
Digital Comparator 3 Trigger.
If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 3 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger.
- If DCMP3 is set, the trigger transitioned to the active state previously.
- If DCMP3 is clear, the trigger has not transitioned to the active state since the last time it was cleared.
- The DCMP3 bit is cleared by writing it with the value 1.
|
| 2 |
DCMP2 |
|
0x0 |
Digital Comparator 2 Trigger.
If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 2 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger.
- If DCMP2 is set, the trigger transitioned to the active state previously.
- If DCMP2 is clear, the trigger has not transitioned to the active state since the last time it was cleared.
- The DCMP2 bit is cleared by writing it with the value 1.
|
| 1 |
DCMP1 |
|
0x0 |
Digital Comparator 1 Trigger.
If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 1 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger.
- If DCMP1 is set, the trigger transitioned to the active state previously.
- If DCMP1 is clear, the trigger has not transitioned to the active state since the last time it was cleared.
- The DCMP1 bit is cleared by writing it with the value 1.
|
| 0 |
DCMP0 |
|
0x0 |
Digital Comparator 0 Trigger.
If the PWMnCTL register LATCH bit is clear, this bit represents the current state of the Digital Comparator 0 trigger input.
If the PWMnCTL register LATCH bit is set, this bit represents a sticky version of the trigger.
- If DCMP0 is set, the trigger transitioned to the active state previously.
- If DCMP0 is clear, the trigger has not transitioned to the active state since the last time it was cleared.
- The DCMP0 bit is cleared by writing it with the value 1.
|