21.5.25 PWMnFLTSRC0 Register [reset = 0x0]
PWM0 Fault Source 0 (PWM0FLTSRC0), offset 0x074
PWM1 Fault Source 0 (PWM1FLTSRC0), offset 0x0B4
PWM2 Fault Source 0 (PWM2FLTSRC0), offset 0x0F4
PWM3 Fault Source 0 (PWM3FLTSRC0), offset 0x134
This register specifies which fault pin inputs are used to generate a fault condition. Each bit in the following register indicates whether the corresponding fault pin is included in the fault condition. All enabled fault pins are ORed together to form the PWMnFLTSRC0 portion of the fault condition. The PWMnFLTSRC0 fault condition is then ORed with the PWMnFLTSRC1 fault condition to generate the final fault condition for the PWM generator.
If the FLTSRC bit in the PWMnCTL register (see Section 21.5.12) is clear, only the Fault0 signal affects the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1 affect the fault condition generated.
PWMnFLTSRC0 is shown in Figure 21-31 and described in Table 21-27.
Return to Summary Table.
Figure 21-31 PWMnFLTSRC0 Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| reserved_2 |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| reserved_2 |
FAULT3 |
FAULT2 |
FAULT1 |
FAULT0 |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 21-27 PWMnFLTSRC0 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-16 |
RESERVED |
R |
0x0 |
|
| 15-4 |
RESERVED |
R |
0x0 |
|
| 3 |
FAULT3 |
R/W |
0x0 |
Fault3 Input. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The Fault3 signal is suppressed and cannot generate a fault condition.
0x1 = The Fault3 signal value is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 2 |
FAULT2 |
R/W |
0x0 |
Fault2 Input. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The Fault2 signal is suppressed and cannot generate a fault condition.
0x1 = The Fault2 signal value is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 1 |
FAULT1 |
R/W |
0x0 |
Fault1 Input. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The Fault1 signal is suppressed and cannot generate a fault condition.
0x1 = The Fault1 signal value is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 0 |
FAULT0 |
R/W |
0x0 |
Fault0 Input. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The Fault0 signal is suppressed and cannot generate a fault condition.
0x1 = The Fault0 signal value is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|