21.5.12 PWMnCTL Register [reset = 0x0]
PWM0 Control (PWM0CTL), offset 0x040
PWM1 Control (PWM1CTL), offset 0x080
PWM2 Control (PWM2CTL), offset 0x0C0
PWM3 Control (PWM3CTL), offset 0x100
These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator 0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable mode are all controlled via these registers. The blocks produce the PWM signals, which can be either two independent PWM signals (from the same counter), or a paired set of PWM signals with dead-band delays added.
The PWM0 block produces the MnPWM0 and MnPWM1 outputs, the PWM1 block produces the MnPWM2 and MnPWM3 outputs, the PWM2 block produces the MnPWM4 and MnPWM5 outputs, and the PWM3 block produces the MnPWM6 and MnPWM7 outputs.
PWMnCTL is shown in Figure 21-18 and described in Table 21-14.
Return to Summary Table.
Figure 21-18 PWMnCTL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
LATCH |
MINFLTPER |
FLTSRC |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| DBFALLUPD |
DBRISEUPD |
DBCTLUPD |
GENBUPD |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| GENAUPD |
CMPBUPD |
CMPAUPD |
LOADUPD |
DEBUG |
MODE |
ENABLE |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 21-14 PWMnCTL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-19 |
RESERVED |
R |
0x0 |
|
| 18 |
LATCH |
R/W |
0x0 |
Latch fault input. When using an ADC digital comparator as a fault source, the LATCH and MINFLTPER bits in the PWMnCTL register should be set to 1 to ensure trigger assertions are captured.
0x0 = Fault Condition Not LatchedA fault condition is in effect for as long as the generating source is asserting.
0x1 = Fault Condition LatchedA fault condition is set as the result of the assertion of the faulting source and is held (latched) while the PWMISC INTFAULTn bit is set. Clearing the INTFAULTn bit clears the fault condition.
|
| 17 |
MINFLTPER |
R/W |
0x0 |
Minimum fault period. This bit specifies that the PWM generator enables a one-shot counter to provide a minimum fault condition period. The timer begins counting on the rising edge of the fault condition to extend the condition for a minimum duration of the count value. The timer ignores the state of the fault condition while counting. The minimum fault delay is in effect only when the MINFLTPER bit is set. If a detected fault is in the process of being extended when the MINFLTPER bit is cleared, the fault condition extension is aborted. The delay time is specified by the PWMnMINFLTPER register MFP field value. The effect of this is to pulse stretch the fault condition input. The delay value is defined by the PWM clock period. Because the fault input is not synchronized to the PWM clock, the period of the time is PWMClock * (MFP value + 1) or PWMClock * (MFP value + 2). The delay function makes sense only if the fault source is unlatched. A latched fault source makes the fault condition appear asserted until cleared by software and negates the utility of the extend feature. It applies to all fault condition sources as specified in the FLTSRC field. When using an ADC digital comparator as a fault source, the LATCH and MINFLTPER bits in the PWMnCTL register should be set to 1 to ensure trigger assertions are captured.
0x0 = The FAULT input deassertion is unaffected.
0x1 = The PWMnMINFLTPER one-shot counter is active and extends the period of the fault condition to a minimum period.
|
| 16 |
FLTSRC |
R/W |
0x0 |
Fault condition source.
0x0 = The Fault condition is determined by the Fault0 input.
0x1 = The Fault condition is determined by the configuration of the PWMnFLTSRC0 and PWMnFLTSRC1 registers.
|
| 15-14 |
DBFALLUPD |
R/W |
0x0 |
PWMnDBFALL update mode
0x0 = ImmediateThe PWMnDBFALL register value is immediately updated on a write.
0x1 = Reserved
0x2 = Locally SynchronizedUpdates to the register are reflected to the generator the next time the counter is 0.
0x3 = Globally SynchronizedUpdates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register.
|
| 13-12 |
DBRISEUPD |
R/W |
0x0 |
PWMnDBRISE update mode.
0x0 = ImmediateThe PWMnDBRISE register value is immediately updated on a write.
0x1 = Reserved
0x2 = Locally SynchronizedUpdates to the register are reflected to the generator the next time the counter is 0.
0x3 = Globally SynchronizedUpdates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register.
|
| 11-10 |
DBCTLUPD |
R/W |
0x0 |
PWMnDBCTL update mode.
0x0 = ImmediateThe PWMnDBCTL register value is immediately updated on a write.
0x1 = Reserved
0x2 = Locally SynchronizedUpdates to the register are reflected to the generator the next time the counter is 0.
0x3 = Globally SynchronizedUpdates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register.
|
| 9-8 |
GENBUPD |
R/W |
0x0 |
PWMnGENB update mode.
0x0 = ImmediateThe PWMnGENB register value is immediately updated on a write.
0x1 = Reserved
0x2 = Locally SynchronizedUpdates to the register are reflected to the generator the next time the counter is 0.
0x3 = Globally SynchronizedUpdates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register.
|
| 7-6 |
GENAUPD |
R/W |
0x0 |
PWMnGENA update mode.
0x0 = Immediate. The PWMnGENA register value is immediately updated on a write.
0x1 = Reserved
0x2 = Locally Synchronized. Updates to the register are reflected to the generator the next time the counter is 0.
0x3 = Globally Synchronized. Updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register.
|
| 5 |
CMPBUPD |
R/W |
0x0 |
Comparator B update mode.
0x0 = Locally SynchronizedUpdates to the PWMnCMPB register are reflected to the generator the next time the counter is 0.
0x1 = Globally SynchronizedUpdates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register.
|
| 4 |
CMPAUPD |
R/W |
0x0 |
Comparator A update mode.
0x0 = Locally SynchronizedUpdates to the PWMnCMPA register are reflected to the generator the next time the counter is 0.
0x1 = Globally SynchronizedUpdates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register.
|
| 3 |
LOADUPD |
R/W |
0x0 |
Load register update mode.
0x0 = Locally SynchronizedUpdates to the PWMnLOAD register are reflected to the generator the next time the counter is 0.
0x1 = Globally SynchronizedUpdates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the PWMCTL register.
|
| 2 |
DEBUG |
R/W |
0x0 |
Debug mode.
0x0 = The counter stops running when it next reaches 0 and continues running again when no longer in Debug mode.
0x1 = The counter always runs when in Debug mode.
|
| 1 |
MODE |
R/W |
0x0 |
Counter mode.
0x0 = The counter counts down from the load value to 0 and then wraps back to the load value (Count-Down mode).
0x1 = The counter counts up from 0 to the load value, back down to 0, and then repeats (Count-Up/Down mode).
|
| 0 |
ENABLE |
R/W |
0x0 |
PWM block enable. Disabling the PWM by clearing the ENABLE bit does not clear the COUNT field of the PWMnCOUNT register. Before re-enabling the PWM (ENABLE = 0x1), the COUNT field should be cleared by resetting the PWM registers through the SRPWM register in the System Control Module.
0x0 = The entire PWM generation block is disabled and not clocked.
0x1 = The PWM generation block is enabled and produces PWM signals.
|