SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PWM0 Compare B (PWM0CMPB), offset 0x05C
PWM1 Compare B (PWM1CMPB), offset 0x09C
PWM2 Compare B (PWM2CMPB), offset 0x0DC
PWM3 Compare B (PWM3CMPB), offset 0x11C
These registers contain a value to be compared against the counter (PWM0CMPB controls the PWM generator 0 block, and so on). When this value matches the counter, a pulse is output which can be configured to drive the generation of the pwmA and pwmB signals (via the PWMnGENA and PWMnGENB registers) or drive an interrupt or ADC trigger (via the PWMnINTEN register). If the value of this register is greater than the PWMnLOAD register, no pulse is ever output.
If the comparator B update mode is locally synchronized (based on the CMPBUPD bit in the PWMnCTL register), the 16-bit COMPB value is used the next time the counter reaches zero. If the update mode is globally synchronized, it is used the next time the counter reaches zero after a synchronous update has been requested through the PWM Master Control (PWMCTL) register (see Section 21.5.1). If this register is rewritten before the actual update occurs, the previous value is never used and is lost.
PWMnCMPB is shown in Figure 21-25 and described in Table 21-21.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | COMPB | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||