21.5.26 PWMnFLTSRC1 Register [reset = 0x0]
PWM0 Fault Source 1 (PWM0FLTSRC1), offset 0x078
PWM1 Fault Source 1 (PWM1FLTSRC1), offset 0x0B8
PWM2 Fault Source 1 (PWM2FLTSRC1), offset 0x0F8
PWM3 Fault Source 1 (PWM3FLTSRC1), offset 0x138
This register specifies which digital comparator triggers from the ADC are used to generate a fault condition. Each bit in the following register indicates whether the corresponding digital comparator trigger is included in the fault condition. All enabled digital comparator triggers are ORed together to form the PWMnFLTSRC1 portion of the fault condition. The PWMnFLTSRC1 fault condition is then ORed with the PWMnFLTSRC0 fault condition to generate the final fault condition for the PWM generator.
If the FLTSRC bit in the PWMnCTL register (see Section 21.5.12) is clear, only the PWM Fault0 pin affects the fault condition generated. Otherwise, sources defined in PWMnFLTSRC0 and PWMnFLTSRC1 affect the fault condition generated.
PWMnFLTSRC1 is shown in Figure 21-32 and described in Table 21-28.
Return to Summary Table.
Figure 21-32 PWMnFLTSRC1 Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| DCMP7 |
DCMP6 |
DCMP5 |
DCMP4 |
DCMP3 |
DCMP2 |
DCMP1 |
DCMP0 |
| R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 21-28 PWMnFLTSRC1 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-8 |
RESERVED |
R |
0x0 |
|
| 7 |
DCMP7 |
R/W |
0x0 |
Digital Comparator 7. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The trigger from digital comparator 7 is suppressed and cannot generate a fault condition.
0x1 = The trigger from digital comparator 7 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 6 |
DCMP6 |
R/W |
0x0 |
Digital Comparator 6. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The trigger from digital comparator 6 is suppressed and cannot generate a fault condition.
0x1 = The trigger from digital comparator 6 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 5 |
DCMP5 |
R/W |
0x0 |
Digital Comparator 5. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The trigger from digital comparator 5 is suppressed and cannot generate a fault condition.
0x1 = The trigger from digital comparator 5 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 4 |
DCMP4 |
R/W |
0x0 |
Digital Comparator 4. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The trigger from digital comparator 4 is suppressed and cannot generate a fault condition.
0x1 = The trigger from digital comparator 4 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 3 |
DCMP3 |
R/W |
0x0 |
Digital Comparator 3. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The trigger from digital comparator 3 is suppressed and cannot generate a fault condition.
0x1 = The trigger from digital comparator 3 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 2 |
DCMP2 |
R/W |
0x0 |
Digital Comparator 2. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The trigger from digital comparator 2 is suppressed and cannot generate a fault condition.
0x1 = The trigger from digital comparator 2 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 1 |
DCMP1 |
R/W |
0x0 |
Digital Comparator 1. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The trigger from digital comparator 1 is suppressed and cannot generate a fault condition.
0x1 = The trigger from digital comparator 1 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|
| 0 |
DCMP0 |
R/W |
0x0 |
Digital Comparator 0. The FLTSRC bit in the PWMnCTL register must be set for this bit to affect fault condition generation.
0x0 = The trigger from digital comparator 0 is suppressed and cannot generate a fault condition.
0x1 = The trigger from digital comparator 0 is ORed with all other fault condition generation inputs (Faultn signals and digital comparators).
|