SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PWM0 Fault Pin Logic Sense (PWM0FLTSEN), offset 0x800
PWM1 Fault Pin Logic Sense (PWM1FLTSEN), offset 0x880
PWM2 Fault Pin Logic Sense (PWM2FLTSEN), offset 0x900
PWM3 Fault Pin Logic Sense (PWM3FLTSEN), offset 0x980
This register defines the PWM fault pin logic sense.
PWMnFLTSEN is shown in Figure 21-34 and described in Table 21-30.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | FAULT3 | FAULT2 | FAULT1 | FAULT0 | |||
R-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||