SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
PWM0 Counter (PWM0COUNT), offset 0x054
PWM1 Counter (PWM1COUNT), offset 0x094
PWM2 Counter (PWM2COUNT), offset 0x0D4
PWM3 Counter (PWM3COUNT), offset 0x114
These registers contain the current value of the PWM counter (PWM0COUNT is the value of the PWM generator 0 block, and so on). When this value matches zero or the value in the PWMnLOAD, PWMnCMPA, or PWMnCMPB registers, a pulse is output which can be configured to drive the generation of a PWM signal or drive an interrupt or ADC trigger.
NOTE
Disabling the PWM by clearing the ENABLE bit does not clear the COUNT field of the PWMnCOUNT register. Before re-enabling the PWM (ENABLE = 0x1), the COUNT field should be cleared by resetting the PWM registers through the SRPWM register in the System Control Module.
PWMnCOUNT is shown in Figure 21-23 and described in Table 21-19.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | COUNT | ||||||||||||||||||||||||||||||
R-0x0 | R-0x0 | ||||||||||||||||||||||||||||||