21.5.29 PWMnFLTSTAT0 Register [reset = 0x0]
PWM0 Fault Status 0 (PWM0FLTSTAT0), offset 0x804
PWM1 Fault Status 0 (PWM1FLTSTAT0), offset 0x884
PWM2 Fault Status 0 (PWM2FLTSTAT0), offset 0x904
PWM3 Fault Status 0 (PWM3FLTSTAT0), offset 0x984
Along with the PWMnFLTSTAT1 register, this register provides status regarding the fault condition inputs.
If the LATCH bit in the PWMnCTL register is clear, the contents of the PWMnFLTSTAT0 register are read-only (R) and provide the current state of the MnFAULTn inputs.
If the LATCH bit in the PWMnCTL register is set, the contents of the PWMnFLTSTAT0 register are read / write 1 to clear (RW1C) and provide a latched version of the MnFAULTn inputs. In this mode, the register bits are cleared by writing a 1 to a set bit. The MnFAULTn inputs are recorded after their sense is adjusted in the generator.
The contents of this register can only be written if the fault source extensions are enabled (the FLTSRC bit in the PWMnCTL register is set).
NOTE
The fault status registers, PWMnFLTSTAT0 and PWMnFLTSTAT1, reflect the status of all fault sources, regardless of what fault sources are enabled for that particular generator.
PWMnFLTSTAT0 is shown in Figure 21-35 and described in Table 21-31.
Return to Summary Table.
Figure 21-35 PWMnFLTSTAT0 Register
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| reserved_1 |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| reserved_1 |
FAULT3 |
FAULT2 |
FAULT1 |
FAULT0 |
| R-0x0 |
0x0 |
0x0 |
0x0 |
0x0 |
|
Table 21-31 PWMnFLTSTAT0 Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 15-4 |
RESERVED |
R |
0x0 |
|
| 3 |
FAULT3 |
|
0x0 |
Fault Input 3.
If the PWMnCTL register LATCH bit is clear, this bit is R and represents the current state of the MnFAULT3 input signal after the logic sense adjustment.
If the PWMnCTL register LATCH bit is set, this bit is RW1C and represents a sticky version of the MnFAULT3 input signal after the logic sense adjustment.
- If FAULT3 is set, the input transitioned to the active state previously.
- If FAULT3 is clear, the input has not transitioned to the active state since the last time it was cleared.
- The FAULT3 bit is cleared by writing it with the value 1.
|
| 2 |
FAULT2 |
|
0x0 |
Fault Input 2.
If the PWMnCTL register LATCH bit is clear, this bit is R and represents the current state of the MnFAULT2 input signal after the logic sense adjustment.
If the PWMnCTL register LATCH bit is set, this bit is RW1C and represents a sticky version of the MnFAULT2 input signal after the logic sense adjustment.
- If FAULT2 is set, the input transitioned to the active state previously.
- If FAULT2 is clear, the input has not transitioned to the active state since the last time it was cleared.
- The FAULT2 bit is cleared by writing it with the value 1.
|
| 1 |
FAULT1 |
|
0x0 |
Fault Input 1.
If the PWMnCTL register LATCH bit is clear, this bit is R and represents the current state of the MnFAULT1 input signal after the logic sense adjustment.
If the PWMnCTL register LATCH bit is set, this bit is RW1C and represents a sticky version of the MnFAULT1 input signal after the logic sense adjustment.
- If FAULT1 is set, the input transitioned to the active state previously.
- If FAULT1 is clear, the input has not transitioned to the active state since the last time it was cleared.
- The FAULT1 bit is cleared by writing it with the value 1.
|
| 0 |
FAULT0 |
|
0x0 |
Fault Input 0.
If the PWMnCTL register LATCH bit is clear, this bit is R and represents the current state of the input signal after the logic sense adjustment.
If the PWMnCTL register LATCH bit is set, this bit is RW1C and represents a sticky version of the input signal after the logic sense adjustment.
- If FAULT0 is set, the input transitioned to the active state previously.
- If FAULT0 is clear, the input has not transitioned to the active state since the last time it was cleared.
- The FAULT0 bit is cleared by writing it with the value 1.
|