21.5.13 PWMnINTEN Register [reset = 0x0]
PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044
PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084
PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4
PWM3 Interrupt and Trigger Enable (PWM3INTEN), offset 0x104
These registers control the interrupt and ADC trigger generation capabilities of the PWM generators (PWM0INTEN controls the PWM generator 0 block, and so on). The events that can cause an interrupt, or an ADC trigger are:
- The counter being equal to the load register
- The counter being equal to zero
- The counter being equal to the PWMnCMPA register while counting up
- The counter being equal to the PWMnCMPA register while counting down
- The counter being equal to the PWMnCMPB register while counting up
- The counter being equal to the PWMnCMPB register while counting down
Any combination of these events can generate either an interrupt or an ADC trigger, though no determination can be made as to the actual event that caused an ADC trigger if more than one is specified. The PWMnRIS register provides information about which events have caused raw interrupts.
PWMnINTEN is shown in Figure 21-19 and described in Table 21-15.
Return to Summary Table.
Figure 21-19 PWMnINTEN Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
TRCMPBD |
TRCMPBU |
TRCMPAD |
TRCMPAU |
TRCNTLOAD |
TRCNTZERO |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
INTCMPBD |
INTCMPBU |
INTCMPAD |
INTCMPAU |
INTCNTLOAD |
INTCNTZERO |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 21-15 PWMnINTEN Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-14 |
RESERVED |
R |
0x0 |
|
| 13 |
TRCMPBD |
R/W |
0x0 |
Trigger for Counter= PWMnCMPB down.
0x0 = No ADC trigger is output.
0x1 = An ADC trigger pulse is output when the counter matches the value in the PWMnCMPB register value while counting down.
|
| 12 |
TRCMPBU |
R/W |
0x0 |
Trigger for Counter= PWMnCMPB up.
0x0 = No ADC trigger is output.
0x1 = An ADC trigger pulse is output when the counter matches the value in the PWMnCMPB register value while counting up.
|
| 11 |
TRCMPAD |
R/W |
0x0 |
Trigger for Counter= PWMnCMPA down.
0x0 = No ADC trigger is output.
0x1 = An ADC trigger pulse is output when the counter matches the value in the PWMnCMPA register value while counting down.
|
| 10 |
TRCMPAU |
R/W |
0x0 |
Trigger for Counter= PWMnCMPA up.
0x0 = No ADC trigger is output.
0x1 = An ADC trigger pulse is output when the counter matches the value in the PWMnCMPA register value while counting up.
|
| 9 |
TRCNTLOAD |
R/W |
0x0 |
Trigger for Counter= PWMnLOAD.
0x0 = No ADC trigger is output.
0x1 = An ADC trigger pulse is output when the counter matches the PWMnLOAD register.
|
| 8 |
TRCNTZERO |
R/W |
0x0 |
Trigger for Counter=0.
0x0 = No ADC trigger is output.
0x1 = An ADC trigger pulse is output when the counter is 0.
|
| 7-6 |
RESERVED |
R |
0x0 |
|
| 5 |
INTCMPBD |
R/W |
0x0 |
Interrupt for Counter= PWMnCMPB down.
0x0 = No interrupt.
0x1 = A raw interrupt occurs when the counter matches the value in the PWMnCMPB register value while counting down.
|
| 4 |
INTCMPBU |
R/W |
0x0 |
Interrupt for Counter= PWMnCMPB up.
0x0 = No interrupt.
0x1 = A raw interrupt occurs when the counter matches the value in the PWMnCMPB register value while counting up.
|
| 3 |
INTCMPAD |
R/W |
0x0 |
Interrupt for Counter= PWMnCMPA down.
0x0 = No interrupt.
0x1 = A raw interrupt occurs when the counter matches the value in the PWMnCMPA register value while counting down.
|
| 2 |
INTCMPAU |
R/W |
0x0 |
Interrupt for Counter= PWMnCMPA up.
0x0 = No interrupt.
0x1 = A raw interrupt occurs when the counter matches the value in the PWMnCMPA register value while counting up.
|
| 1 |
INTCNTLOAD |
R/W |
0x0 |
Interrupt for Counter= PWMnLOAD.
0x0 = No interrupt.
0x1 = A raw interrupt occurs when the counter matches the value in the PWMnLOAD register value.
|
| 0 |
INTCNTZERO |
R/W |
0x0 |
Interrupt for Counter=0.
0x0 = No interrupt.
0x1 = A raw interrupt occurs when the counter is zero.
|