6.3.5.1 RTC Counter - Seconds/Subseconds Mode

The clock signal to the RTC is provided by either of the 32.768-kHz clock sources available to the Hibernation module. The Hibernation RTC Counter (HIBRTCC) register displays the seconds value. The Hibernation RTC Sub Seconds register (HIBRTCSS) is provided for additional time resolution of an application requiring less than one-second divisions.

The RTC is enabled by setting the RTCEN bit of the HIBCTL register. The RTCEN bit is also used along with the CALEN bit in the Hibernation Calendar Control (HIBCALCTL) register to enable the calender. Thus, if the calendar is enabled, the RTC registers, HIBRTCC, HIBRTCSS, HIBRTCM0 and HIBRTCLD, cannot be used. The RTC counter and subseconds counters begin counting immediately when RTCEN is set. Both counters count up. The RTC continues counting as long as the RTC is enabled and a valid V_BAT is present, regardless of whether V_DD is present or if the device is in hibernation.

The HIBRTCC register is set by writing the Hibernation RTC Load (HIBRTCLD) register. A write to the HIBRTCLD register clears the 15-bit subseconds counter field, RTCSSC, in the HIBRTCSS register. To ensure a valid read of the RTC value, the HIBRTCC register should be read first, followed by a read of the RTCSSC field in the HIBRTCSS register and then a re-read of the HIBRTCC register. If the two values for the HIBRTCC are equal, the read is valid. By following this procedure, errors in the application caused by the HIBRTCC register rolling over by a count of 1 during a read of the RTCSSC field are prevented. The RTC can be configured to generate an alarm by setting the RTCAL0 bit in the HIBIM register. When an RTC match occurs, an interrupt is generated and displayed in the HIBRIS register. Refer to Section 6.3.5.2 for more information.

If the RTC is enabled, only a cold POR, where both V_BAT and V_DD are removed, resets the RTC registers. If any other reset occurs while the RTC is enabled, such as an external RST assertion or BOR reset, the RTC is not reset. The RTC registers can be reset under any type of system reset as long as the RTC, external wake pins and tamper pins are not enabled.

A buffered version of the 32.768-kHz signal Hibernate clock source is available on the RTCCLK signal output, which is muxed with a GPIO pin. The RTCCLK signal can be the external 32.786-kHz clock source or the HIB LFIOSC depending on the value of the OSCSEL bit in the HIBCTL register. See or pin mux information and Section 17 for additional details on initialization and configuration of this signal. The pin does not output RTCCLK when Hibernate mode is active or before the RTCCLK GPIO digital function has been selected through the GPIO Digital Enable (GPIODEN) register in the GPIO module. This includes selecting the RTCCLK signal as an output source in the GPIO Port Control (GPIOPCTL) register and setting the SYSCLKEN bit within the Hibernate Clock Control (HIBCC) register.