SLPU010 September   2022 JFE2140

 

  1.   Abstract
  2.   Trademarks
  3. 1Overview
    1. 1.1 JFE2140 Overview
    2. 1.2 JFE2140EVM Overview
      1. 1.2.1 Kit Contents
    3. 1.3 Related Documentation
    4. 1.4 Evaluation Module Limitations
    5. 1.5 Electrostatic Discharge Caution
  4. 2Getting Started
    1. 2.1 Power Supplies
    2. 2.2 Input
    3. 2.3 Output
    4. 2.4 Capacitors
  5. 3Application Circuit
    1. 3.1 Ultra-Low-Noise Preamplifier
  6. 4Schematic, PCB Layout, and Bill of Materials
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 Bill of Materials

PCB Layout

GUID-20220818-SS0I-RRM3-HWXC-5CLZXQ8BR9GB-low.png Figure 4-2 JFE2140EVM PCB Layout
GUID-20220818-SS0I-TJTZ-85NB-JFXSQ6VPNSCF-low.png Figure 4-3 JFE2140EVM Top Overlay
GUID-20220818-SS0I-TJMF-QXJD-NNBSNT8XPBH1-low.png Figure 4-4 JFE2140EVM Top Solder Mask
GUID-20220818-SS0I-DGHS-Z9LV-9PRSPRQV9R4N-low.png Figure 4-5 JFE2140EVM Top Layer
GUID-20220818-SS0I-FLM3-G2V5-4D2QNCH6QSZ3-low.png Figure 4-6 JFE2140EVM Signal Layer 1
GUID-20220818-SS0I-JJKG-D7LZ-P5GB1F4SGMTJ-low.png Figure 4-7 JFE2140EVM Signal Layer 2
GUID-20220818-SS0I-CVCB-KG8T-QPJ1H5CTSMB4-low.png Figure 4-8 JFE2140EVM Bottom Layer
GUID-20220818-SS0I-JLMK-WLFV-LLQSQXPSK0DK-low.png Figure 4-9 JFE2140EVM Bottom Solder Mask
GUID-20220818-SS0I-C521-G090-Z1JXSWMZ3CQ7-low.png Figure 4-10 JFE2140EVM Drill Drawing
GUID-20220818-SS0I-CLPW-87NS-CQR1DGDK68JW-low.png Figure 4-11 JFE2140EVM Board Dimensions