Figure 3-1 shows a simplified schematic of the EVM for the purpose of this application circuit. Figure 4-1 shows the full default configuration of the JFE2140EVM. The EVM operates on a split supply of VDD = 5 V and VSS = –5 V. The output voltage, Vout, settles to approximately midsupply ±2 V.

Figure 3-1 shows that tail current I_Tail ≅ 2 mA. This figure also shows that resistors R37 and R15 form the beta feedback network that provides a closed-loop gain of 1001 V/V, or approximately 60 dB. Figure 3-2 shows the result. The high gain provided by the EVM is designed for small-signal amplification, but can also be used to measure the low V_GS mismatch of the JFE2140. A V_GS mismatch of 1 mV results in a dc output voltage of 1 V.

Figure 4-1 shows an optional integrator circuit using the OPA145 that helps reduce V_GS mismatch. The integrator circuit monitors both gates of the JFE2140 and feeds back a current to one drain. The integrator circuit path uses components U3A, R39-R42, R44, R45, and C16–C18. Make sure that resistor R42 is large enough to maintain the dc bias voltage of the drain on JFET Q1B. The EVM default configuration uses SMA connector J8 for single-in and single-out signal amplification. XLR connectors Vdiff_In and Vdiff_Out are provided as an option for differential-signal amplification. When using the EVM for differential-signal amplification, remove composite amplifier U1A and resistors R37 and R15. Component footprints R18, R14, and C4 are provided for the second input. A path for earth ground is provided through resistor R43.