The input to the JFE2140EVM interfaces high-impedance sources to the gate of the JFET. The input is ac-coupled with capacitor C3, and the dc gate bias voltage is set with resistor R13. A single SMA connector and Vin test point are available at the input to allow for an easy interface with signal generators or other equipment. Figure 3-2 shows that the midband gain of the circuit is approximately 1000 V/V or 60 dB. For example, a 1-mVpp, 1-kHz input signal produces an approximately 1-Vpp, 1-kHz signal measured on the output. The Design tools and simulation tab on the JFE2140 web folder assists with other configurations.