SLUUCF2C January   2021  – May 2022 BQ769142

 

  1.   Read This First
    1.     Battery Monitor Notational Conventions
    2.     Trademarks
    3.     Glossary
  2. 1 Introduction
  3. 2 Device Description
    1. 2.1 Overview
    2. 2.2 Functional Block Diagram
  4. 3 Device Configuration
    1. 3.1 Direct Commands and Subcommands
    2. 3.2 Configuration Using OTP or Registers
    3. 3.3 Data Formats
      1. 3.3.1 Unsigned Integer
      2. 3.3.2 Integer
      3. 3.3.3 Floating Point
      4. 3.3.4 Hex
  5. 4 Measurement Subsystem
    1. 4.1  Voltage Measurement
      1. 4.1.1 Voltage Measurement Schedule
      2. 4.1.2 Usage of VC Pins for Cells Versus Interconnect
      3. 4.1.3 Cell Interconnect Resistance
    2. 4.2  General Purpose ADCIN Functionality
    3. 4.3  Coulomb Counter and Digital Filters
    4. 4.4  Synchronized Voltage and Current Measurement
    5. 4.5  Subcommands 0x0071–0x0074 DASTATUS1-4(), Cell Voltage and Synchronized Current Counts
    6. 4.6  Subcommands 0x0075–0x0077 DASTATUS5–7(), Additional Measurements
    7. 4.7  Internal Temperature Measurement
    8. 4.8  Thermistor Temperature Measurement
    9. 4.9  Factory Trim of Voltage ADC
    10. 4.10 Voltage Calibration (ADC Measurements)
    11. 4.11 Voltage Calibration (COV and CUV Protections)
    12. 4.12 Current Calibration
    13. 4.13 Temperature Calibration
  6. 5 Primary and Secondary Protection Subsystems
    1. 5.1 Protections Overview
    2. 5.2 Primary Protections
      1. 5.2.1  Primary Protections Overview
      2. 5.2.2  High-Side NFET Drivers
      3. 5.2.3  Protection FETs Configuration and Control
        1. 5.2.3.1 FET Configuration
        2. 5.2.3.2 FET Control
          1. 5.2.3.2.1 PRECHARGE Mode
          2. 5.2.3.2.2 PREDISCHARGE Mode
      4. 5.2.4  Cell Overvoltage Protection
      5. 5.2.5  Cell Undervoltage Protection
      6. 5.2.6  Short Circuit in Discharge Protection
      7. 5.2.7  Overcurrent in Charge Protection
      8. 5.2.8  Overcurrent in Discharge 1, 2, and 3 Protections
      9. 5.2.9  Overtemperature in Charge Protection
      10. 5.2.10 Overtemperature in Discharge Protection
      11. 5.2.11 Overtemperature FET Protection
      12. 5.2.12 Internal Overtemperature Protection
      13. 5.2.13 Undertemperature in Charge Protection
      14. 5.2.14 Undertemperature in Discharge Protection
      15. 5.2.15 Internal Undertemperature Protection
      16. 5.2.16 Host Watchdog Protection
      17. 5.2.17 Precharge Timeout Protection
      18. 5.2.18 Load Detect Functionality
    3. 5.3 Secondary Protections
      1. 5.3.1  Secondary Protections Overview
      2. 5.3.2  Copper Deposition (CUDEP) Permanent Fail
      3. 5.3.3  Safety Undervoltage (SUV) Permanent Fail
      4. 5.3.4  Safety Overvoltage (SOV) Permanent Fail
      5. 5.3.5  Safety Overcurrent in Charge (SOCC) Permanent Fail
      6. 5.3.6  Safety Overcurrent in Discharge (SOCD) Permanent Fail
      7. 5.3.7  Safety Cell Overtemperature (SOT) Permanent Fail
      8. 5.3.8  Safety FET Overtemperature (SOTF) Permanent Fail
      9. 5.3.9  Charge FET (CFETF) Permanent Fail
      10. 5.3.10 Discharge FET (DFETF) Permanent Fail
      11. 5.3.11 Secondary Protector (2LVL) Permanent Fail
      12. 5.3.12 Voltage Imbalance in Relax (VIMR) Permanent Fail
      13. 5.3.13 Voltage Imbalance in Active (VIMA) Permanent Fail
      14. 5.3.14 Short Circuit in Discharge Latched Permanent Fail
      15. 5.3.15 OTP Memory Signature Permanent Fail
      16. 5.3.16 Data ROM Memory Signature Permanent Fail
      17. 5.3.17 Instruction ROM Memory Signature Permanent Fail
      18. 5.3.18 LFO Oscillator Permanent Fail
      19. 5.3.19 Voltage Reference Permanent Fail
      20. 5.3.20 VSS Permanent Fail
      21. 5.3.21 Protection Comparator MUX Permanent Fail
      22. 5.3.22 Commanded Permanent Fail
      23. 5.3.23 Top of Stack Measurement Check
      24. 5.3.24 Cell Open Wire
  7. 6 Device Status and Controls
    1. 6.1 0x00 Control Status() and 0x12 Battery Status() Commands
    2. 6.2 0x0070 MANU_DATA() Subcommand
    3. 6.3 LDOs
      1. 6.3.1 Preregulator Control
      2. 6.3.2 REG1 and REG2 LDO Controls
    4. 6.4 Multifunction Pin Controls
    5. 6.5 CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
    6. 6.6 ALERT Pin Operation
    7. 6.7 DDSG and DCHG Pin Operation
    8. 6.8 Fuse Drive
    9. 6.9 Device Event Timing
  8. 7 Operational Modes
    1. 7.1 Overview
    2. 7.2 NORMAL Mode
    3. 7.3 SLEEP Mode
    4. 7.4 DEEPSLEEP Mode
    5. 7.5 SHUTDOWN Mode
    6. 7.6 CONFIG_UPDATE Mode
  9. 8 Device Security
    1. 8.1 Overview
  10. 9 Serial Communications Interfaces
    1. 9.1 Serial Communications Overview
    2. 9.2 I2C Communications Subsystem
    3. 9.3 SPI Communications Interface
      1. 9.3.1 SPI Protocol
    4. 9.4 HDQ Communications Interface
  11. 10Cell Balancing
    1. 10.1 Cell Balancing Operation
    2. 10.2 Cell Balancing Timing
  12. 11Diagnostics
    1. 11.1 Diagnostics Overview
    2. 11.2 VREF2 Versus VREF1 Check
    3. 11.3 VSS Measurement
    4. 11.4 Top of Stack Measurement Check
    5. 11.5 LFO Oscillator Monitor
    6. 11.6 Protection Comparator Mux Check
    7. 11.7 Internal Watchdog Reset
    8. 11.8 Internal Memory Checks
  13. 12Commands and Subcommands
    1. 12.1 Direct Commands
    2. 12.2 Bitfield Definitions for Direct Commands
      1. 12.2.1  Control Status Register
      2. 12.2.2  Safety Alert A Register
      3. 12.2.3  Safety Status A Register
      4. 12.2.4  Safety Alert B Register
      5. 12.2.5  Safety Status B Register
      6. 12.2.6  Safety Alert C Register
      7. 12.2.7  Safety Status C Register
      8. 12.2.8  PF Alert A Register
      9. 12.2.9  PF Status A Register
      10. 12.2.10 PF Alert B Register
      11. 12.2.11 PF Status B Register
      12. 12.2.12 PF Alert C Register
      13. 12.2.13 PF Status C Register
      14. 12.2.14 PF Alert D Register
      15. 12.2.15 PF Status D Register
      16. 12.2.16 Battery Status Register
      17. 12.2.17 Alarm Status Register
      18. 12.2.18 Alarm Raw Status Register
      19. 12.2.19 Alarm Enable Register
      20. 12.2.20 FET Status Register
    3. 12.3 Command-Only Subcommands
    4. 12.4 Subcommands with Data
    5. 12.5 Bitfield Definitions for Subcommands
      1. 12.5.1 PF Status A Register
      2. 12.5.2 PF Status B Register
      3. 12.5.3 PF Status C Register
      4. 12.5.4 PF Status D Register
      5. 12.5.5 Manufacturing Status Register
      6. 12.5.6 FET Control Register
      7. 12.5.7 REG12 Control Register
      8. 12.5.8 OTP Write Check Result Register
      9. 12.5.9 OTP Write Result Register
  14. 13Data Memory Settings
    1. 13.1 Data Memory Access
    2. 13.2 Calibration
      1. 13.2.1  Calibration:Voltage
        1. 13.2.1.1  Calibration:Voltage:Cell 1 Gain
        2. 13.2.1.2  Calibration:Voltage:Cell 2 Gain
        3. 13.2.1.3  Calibration:Voltage:Cell 3 Gain
        4. 13.2.1.4  Calibration:Voltage:Cell 4 Gain
        5. 13.2.1.5  Calibration:Voltage:Cell 5 Gain
        6. 13.2.1.6  Calibration:Voltage:Cell 6 Gain
        7. 13.2.1.7  Calibration:Voltage:Cell 7 Gain
        8. 13.2.1.8  Calibration:Voltage:Cell 8 Gain
        9. 13.2.1.9  Calibration:Voltage:Cell 9 Gain
        10. 13.2.1.10 Calibration:Voltage:Cell 10 Gain
        11. 13.2.1.11 Calibration:Voltage:Cell 11 Gain
        12. 13.2.1.12 Calibration:Voltage:Cell 12 Gain
        13. 13.2.1.13 Calibration:Voltage:Cell 13 Gain
        14. 13.2.1.14 Calibration:Voltage:Cell 14 Gain
        15. 13.2.1.15 Calibration:Voltage:Pack Gain
        16. 13.2.1.16 Calibration:Voltage:TOS Gain
        17. 13.2.1.17 Calibration:Voltage:LD Gain
        18. 13.2.1.18 Calibration:Voltage:ADC Gain
      2. 13.2.2  Calibration:Current
        1. 13.2.2.1 Calibration:Current:CC Gain
        2. 13.2.2.2 Calibration:Current:Capacity Gain
      3. 13.2.3  Calibration:Vcell Offset
        1. 13.2.3.1 Calibration:Vcell Offset:Vcell Offset
      4. 13.2.4  Calibration:V Divider Offset
        1. 13.2.4.1 Calibration:V Divider Offset:Vdiv Offset
      5. 13.2.5  Calibration:Current Offset
        1. 13.2.5.1 Calibration:Current Offset:Coulomb Counter Offset Samples
        2. 13.2.5.2 Calibration:Current Offset:Board Offset
      6. 13.2.6  Calibration:Temperature
        1. 13.2.6.1  Calibration:Temperature:Internal Temp Offset
        2. 13.2.6.2  Calibration:Temperature:CFETOFF Temp Offset
        3. 13.2.6.3  Calibration:Temperature:DFETOFF Temp Offset
        4. 13.2.6.4  Calibration:Temperature:ALERT Temp Offset
        5. 13.2.6.5  Calibration:Temperature:TS1 Temp Offset
        6. 13.2.6.6  Calibration:Temperature:TS2 Temp Offset
        7. 13.2.6.7  Calibration:Temperature:TS3 Temp Offset
        8. 13.2.6.8  Calibration:Temperature:HDQ Temp Offset
        9. 13.2.6.9  Calibration:Temperature:DCHG Temp Offset
        10. 13.2.6.10 Calibration:Temperature:DDSG Temp Offset
      7. 13.2.7  Calibration:Internal Temp Model
        1. 13.2.7.1 Calibration:Internal Temp Model:Int Gain
        2. 13.2.7.2 Calibration:Internal Temp Model:Int base offset
        3. 13.2.7.3 Calibration:Internal Temp Model:Int Maximum AD
        4. 13.2.7.4 Calibration:Internal Temp Model:Int Maximum Temp
      8. 13.2.8  Calibration:18K Temperature Model
        1. 13.2.8.1  Calibration:18K Temperature Model:Coeff a1
        2. 13.2.8.2  Calibration:18K Temperature Model:Coeff a2
        3. 13.2.8.3  Calibration:18K Temperature Model:Coeff a3
        4. 13.2.8.4  Calibration:18K Temperature Model:Coeff a4
        5. 13.2.8.5  Calibration:18K Temperature Model:Coeff a5
        6. 13.2.8.6  Calibration:18K Temperature Model:Coeff b1
        7. 13.2.8.7  Calibration:18K Temperature Model:Coeff b2
        8. 13.2.8.8  Calibration:18K Temperature Model:Coeff b3
        9. 13.2.8.9  Calibration:18K Temperature Model:Coeff b4
        10. 13.2.8.10 Calibration:18K Temperature Model:Adc0
      9. 13.2.9  Calibration:180K Temperature Model
        1. 13.2.9.1  Calibration:180K Temperature Model:Coeff a1
        2. 13.2.9.2  Calibration:180K Temperature Model:Coeff a2
        3. 13.2.9.3  Calibration:180K Temperature Model:Coeff a3
        4. 13.2.9.4  Calibration:180K Temperature Model:Coeff a4
        5. 13.2.9.5  Calibration:180K Temperature Model:Coeff a5
        6. 13.2.9.6  Calibration:180K Temperature Model:Coeff b1
        7. 13.2.9.7  Calibration:180K Temperature Model:Coeff b2
        8. 13.2.9.8  Calibration:180K Temperature Model:Coeff b3
        9. 13.2.9.9  Calibration:180K Temperature Model:Coeff b4
        10. 13.2.9.10 Calibration:180K Temperature Model:Adc0
      10. 13.2.10 Calibration:Custom Temperature Model
        1. 13.2.10.1  Calibration:Custom Temperature Model:Coeff a1
        2. 13.2.10.2  Calibration:Custom Temperature Model:Coeff a2
        3. 13.2.10.3  Calibration:Custom Temperature Model:Coeff a3
        4. 13.2.10.4  Calibration:Custom Temperature Model:Coeff a4
        5. 13.2.10.5  Calibration:Custom Temperature Model:Coeff a5
        6. 13.2.10.6  Calibration:Custom Temperature Model:Coeff b1
        7. 13.2.10.7  Calibration:Custom Temperature Model:Coeff b2
        8. 13.2.10.8  Calibration:Custom Temperature Model:Coeff b3
        9. 13.2.10.9  Calibration:Custom Temperature Model:Coeff b4
        10. 13.2.10.10 Calibration:Custom Temperature Model:Rc0
        11. 13.2.10.11 Calibration:Custom Temperature Model:Adc0
      11. 13.2.11 Calibration:Current Deadband
        1. 13.2.11.1 Calibration:Current Deadband:Coulomb Counter Deadband
      12. 13.2.12 Calibration:CUV
        1. 13.2.12.1 Calibration:CUV:CUV Threshold Override
      13. 13.2.13 Calibration:COV
        1. 13.2.13.1 Calibration:COV:COV Threshold Override
    3. 13.3 Settings
      1. 13.3.1  Settings:Fuse
        1. 13.3.1.1 Settings:Fuse:Min Blow Fuse Voltage
        2. 13.3.1.2 Settings:Fuse:Fuse Blow Timeout
      2. 13.3.2  Settings:Configuration
        1. 13.3.2.1  Settings:Configuration:Power Config
        2. 13.3.2.2  Settings:Configuration:REG12 Config
        3. 13.3.2.3  Settings:Configuration:REG0 Config
        4. 13.3.2.4  Settings:Configuration:HWD Regulator Options
        5. 13.3.2.5  Settings:Configuration:Comm Type
        6. 13.3.2.6  Settings:Configuration:I2C Address
        7. 13.3.2.7  Settings:Configuration:SPI Configuration
        8. 13.3.2.8  Settings:Configuration:Comm Idle Time
        9. 13.3.2.9  Settings:Configuration:CFETOFF Pin Config
        10. 13.3.2.10 Settings:Configuration:DFETOFF Pin Config
        11. 13.3.2.11 Settings:Configuration:ALERT Pin Config
        12. 13.3.2.12 Settings:Configuration:TS1 Config
        13. 13.3.2.13 Settings:Configuration:TS2 Config
        14. 13.3.2.14 Settings:Configuration:TS3 Config
        15. 13.3.2.15 Settings:Configuration:HDQ Pin Config
        16. 13.3.2.16 Settings:Configuration:DCHG Pin Config
        17. 13.3.2.17 Settings:Configuration:DDSG Pin Config
        18. 13.3.2.18 Settings:Configuration:DA Configuration
        19. 13.3.2.19 Settings:Configuration:Vcell Mode
        20. 13.3.2.20 Settings:Configuration:CC3 Samples
      3. 13.3.3  Settings:Protection
        1. 13.3.3.1  Settings:Protection:Protection Configuration
        2. 13.3.3.2  Settings:Protection:Enabled Protections A
        3. 13.3.3.3  Settings:Protection:Enabled Protections B
        4. 13.3.3.4  Settings:Protection:Enabled Protections C
        5. 13.3.3.5  Settings:Protection:CHG FET Protections A
        6. 13.3.3.6  Settings:Protection:CHG FET Protections B
        7. 13.3.3.7  Settings:Protection:CHG FET Protections C
        8. 13.3.3.8  Settings:Protection:DSG FET Protections A
        9. 13.3.3.9  Settings:Protection:DSG FET Protections B
        10. 13.3.3.10 Settings:Protection:DSG FET Protections C
        11. 13.3.3.11 Settings:Protection:Body Diode Threshold
      4. 13.3.4  Settings:Alarm
        1. 13.3.4.1 Settings:Alarm:Default Alarm Mask
        2. 13.3.4.2 Settings:Alarm:SF Alert Mask A
        3. 13.3.4.3 Settings:Alarm:SF Alert Mask B
        4. 13.3.4.4 Settings:Alarm:SF Alert Mask C
        5. 13.3.4.5 Settings:Alarm:PF Alert Mask A
        6. 13.3.4.6 Settings:Alarm:PF Alert Mask B
        7. 13.3.4.7 Settings:Alarm:PF Alert Mask C
        8. 13.3.4.8 Settings:Alarm:PF Alert Mask D
      5. 13.3.5  Settings:Permanent Failure
        1. 13.3.5.1 Settings:Permanent Failure:Enabled PF A
        2. 13.3.5.2 Settings:Permanent Failure:Enabled PF B
        3. 13.3.5.3 Settings:Permanent Failure:Enabled PF C
        4. 13.3.5.4 Settings:Permanent Failure:Enabled PF D
      6. 13.3.6  Settings:FET
        1. 13.3.6.1 Settings:FET:FET Options
        2. 13.3.6.2 Settings:FET:Chg Pump Control
        3. 13.3.6.3 Settings:FET:Precharge Start Voltage
        4. 13.3.6.4 Settings:FET:Precharge Stop Voltage
        5. 13.3.6.5 Settings:FET:Predischarge Timeout
        6. 13.3.6.6 Settings:FET:Predischarge Stop Delta
      7. 13.3.7  Settings:Current Thresholds
        1. 13.3.7.1 Settings:Current Thresholds:Dsg Current Threshold
        2. 13.3.7.2 Settings:Current Thresholds:Chg Current Threshold
      8. 13.3.8  Settings:Cell Open-Wire
        1. 13.3.8.1 Settings:Cell Open-Wire:Check Time
      9. 13.3.9  Settings:Interconnect Resistances
        1. 13.3.9.1  Settings:Interconnect Resistances:Cell 1 Interconnect
        2. 13.3.9.2  Settings:Interconnect Resistances:Cell 2 Interconnect
        3. 13.3.9.3  Settings:Interconnect Resistances:Cell 3 Interconnect
        4. 13.3.9.4  Settings:Interconnect Resistances:Cell 4 Interconnect
        5. 13.3.9.5  Settings:Interconnect Resistances:Cell 5 Interconnect
        6. 13.3.9.6  Settings:Interconnect Resistances:Cell 6 Interconnect
        7. 13.3.9.7  Settings:Interconnect Resistances:Cell 7 Interconnect
        8. 13.3.9.8  Settings:Interconnect Resistances:Cell 8 Interconnect
        9. 13.3.9.9  Settings:Interconnect Resistances:Cell 9 Interconnect
        10. 13.3.9.10 Settings:Interconnect Resistances:Cell 10 Interconnect
        11. 13.3.9.11 Settings:Interconnect Resistances:Cell 11 Interconnect
        12. 13.3.9.12 Settings:Interconnect Resistances:Cell 12 Interconnect
        13. 13.3.9.13 Settings:Interconnect Resistances:Cell 13 Interconnect
        14. 13.3.9.14 Settings:Interconnect Resistances:Cell 14 Interconnect
      10. 13.3.10 Settings:Manufacturing
        1. 13.3.10.1 Settings:Manufacturing:Mfg Status Init
      11. 13.3.11 Settings:Cell Balancing Config
        1. 13.3.11.1  Settings:Cell Balancing Config:Balancing Configuration
        2. 13.3.11.2  Settings:Cell Balancing Config:Min Cell Temp
        3. 13.3.11.3  Settings:Cell Balancing Config:Max Cell Temp
        4. 13.3.11.4  Settings:Cell Balancing Config:Max Internal Temp
        5. 13.3.11.5  Settings:Cell Balancing Config:Cell Balance Interval
        6. 13.3.11.6  Settings:Cell Balancing Config:Cell Balance Max Cells
        7. 13.3.11.7  Settings:Cell Balancing Config:Cell Balance Min Cell V (Charge)
        8. 13.3.11.8  Settings:Cell Balancing Config:Cell Balance Min Delta (Charge)
        9. 13.3.11.9  Settings:Cell Balancing Config:Cell Balance Stop Delta (Charge)
        10. 13.3.11.10 Settings:Cell Balancing Config:Cell Balance Min Cell V (Relax)
        11. 13.3.11.11 Settings:Cell Balancing Config:Cell Balance Min Delta (Relax)
        12. 13.3.11.12 Settings:Cell Balancing Config:Cell Balance Stop Delta (Relax)
    4. 13.4 Power
      1. 13.4.1 Power:Shutdown
        1. 13.4.1.1 Power:Shutdown:Shutdown Cell Voltage
        2. 13.4.1.2 Power:Shutdown:Shutdown Stack Voltage
        3. 13.4.1.3 Power:Shutdown:Low V Shutdown Delay
        4. 13.4.1.4 Power:Shutdown:Shutdown Temperature
        5. 13.4.1.5 Power:Shutdown:Shutdown Temperature Delay
        6. 13.4.1.6 Power:Shutdown:FET Off Delay
        7. 13.4.1.7 Power:Shutdown:Shutdown Command Delay
        8. 13.4.1.8 Power:Shutdown:Auto Shutdown Time
        9. 13.4.1.9 Power:Shutdown:RAM Fail Shutdown Time
      2. 13.4.2 Power:Sleep
        1. 13.4.2.1 Power:Sleep:Sleep Current
        2. 13.4.2.2 Power:Sleep:Voltage Time
        3. 13.4.2.3 Power:Sleep:Wake Comparator Current
        4. 13.4.2.4 Power:Sleep:Sleep Hysteresis Time
        5. 13.4.2.5 Power:Sleep:Sleep Charger Voltage Threshold
        6. 13.4.2.6 Power:Sleep:Sleep Charger PACK-TOS Delta
    5. 13.5 System Data
      1. 13.5.1 System Data:Integrity
        1. 13.5.1.1 System Data:Integrity:Config RAM Signature
    6. 13.6 Protections
      1. 13.6.1  Protections:CUV
        1. 13.6.1.1 Protections:CUV:Threshold
        2. 13.6.1.2 Protections:CUV:Delay
        3. 13.6.1.3 Protections:CUV:Recovery Hysteresis
      2. 13.6.2  Protections:COV
        1. 13.6.2.1 Protections:COV:Threshold
        2. 13.6.2.2 Protections:COV:Delay
        3. 13.6.2.3 Protections:COV:Recovery Hysteresis
      3. 13.6.3  Protections:COVL
        1. 13.6.3.1 Protections:COVL:Latch Limit
        2. 13.6.3.2 Protections:COVL:Counter Dec Delay
        3. 13.6.3.3 Protections:COVL:Recovery Time
      4. 13.6.4  Protections:OCC
        1. 13.6.4.1 Protections:OCC:Threshold
        2. 13.6.4.2 Protections:OCC:Delay
        3. 13.6.4.3 Protections:OCC:Recovery Threshold
        4. 13.6.4.4 Protections:OCC:PACK-TOS Delta
      5. 13.6.5  Protections:OCD1
        1. 13.6.5.1 Protections:OCD1:Threshold
        2. 13.6.5.2 Protections:OCD1:Delay
      6. 13.6.6  Protections:OCD2
        1. 13.6.6.1 Protections:OCD2:Threshold
        2. 13.6.6.2 Protections:OCD2:Delay
      7. 13.6.7  Protections:SCD
        1. 13.6.7.1 Protections:SCD:Threshold
        2. 13.6.7.2 Protections:SCD:Delay
        3. 13.6.7.3 Protections:SCD:Recovery Time
      8. 13.6.8  Protections:OCD3
        1. 13.6.8.1 Protections:OCD3:Threshold
        2. 13.6.8.2 Protections:OCD3:Delay
      9. 13.6.9  Protections:OCD
        1. 13.6.9.1 Protections:OCD:Recovery Threshold
      10. 13.6.10 Protections:OCDL
        1. 13.6.10.1 Protections:OCDL:Latch Limit
        2. 13.6.10.2 Protections:OCDL:Counter Dec Delay
        3. 13.6.10.3 Protections:OCDL:Recovery Time
        4. 13.6.10.4 Protections:OCDL:Recovery Threshold
      11. 13.6.11 Protections:SCDL
        1. 13.6.11.1 Protections:SCDL:Latch Limit
        2. 13.6.11.2 Protections:SCDL:Counter Dec Delay
        3. 13.6.11.3 Protections:SCDL:Recovery Time
        4. 13.6.11.4 Protections:SCDL:Recovery Threshold
      12. 13.6.12 Protections:OTC
        1. 13.6.12.1 Protections:OTC:Threshold
        2. 13.6.12.2 Protections:OTC:Delay
        3. 13.6.12.3 Protections:OTC:Recovery
      13. 13.6.13 Protections:OTD
        1. 13.6.13.1 Protections:OTD:Threshold
        2. 13.6.13.2 Protections:OTD:Delay
        3. 13.6.13.3 Protections:OTD:Recovery
      14. 13.6.14 Protections:OTF
        1. 13.6.14.1 Protections:OTF:Threshold
        2. 13.6.14.2 Protections:OTF:Delay
        3. 13.6.14.3 Protections:OTF:Recovery
      15. 13.6.15 Protections:OTINT
        1. 13.6.15.1 Protections:OTINT:Threshold
        2. 13.6.15.2 Protections:OTINT:Delay
        3. 13.6.15.3 Protections:OTINT:Recovery
      16. 13.6.16 Protections:UTC
        1. 13.6.16.1 Protections:UTC:Threshold
        2. 13.6.16.2 Protections:UTC:Delay
        3. 13.6.16.3 Protections:UTC:Recovery
      17. 13.6.17 Protections:UTD
        1. 13.6.17.1 Protections:UTD:Threshold
        2. 13.6.17.2 Protections:UTD:Delay
        3. 13.6.17.3 Protections:UTD:Recovery
      18. 13.6.18 Protections:UTINT
        1. 13.6.18.1 Protections:UTINT:Threshold
        2. 13.6.18.2 Protections:UTINT:Delay
        3. 13.6.18.3 Protections:UTINT:Recovery
      19. 13.6.19 Protections:Recovery
        1. 13.6.19.1 Protections:Recovery:Time
      20. 13.6.20 Protections:HWD
        1. 13.6.20.1 Protections:HWD:Delay
      21. 13.6.21 Protections:Load Detect
        1. 13.6.21.1 Protections:Load Detect:Active Time
        2. 13.6.21.2 Protections:Load Detect:Retry Delay
        3. 13.6.21.3 Protections:Load Detect:Timeout
      22. 13.6.22 Protections:PTO
        1. 13.6.22.1 Protections:PTO:Charge Threshold
        2. 13.6.22.2 Protections:PTO:Delay
        3. 13.6.22.3 Protections:PTO:Reset
    7. 13.7 Permanent Fail
      1. 13.7.1  Permanent Fail:CUDEP
        1. 13.7.1.1 Permanent Fail:CUDEP:Threshold
        2. 13.7.1.2 Permanent Fail:CUDEP:Delay
      2. 13.7.2  Permanent Fail:SUV
        1. 13.7.2.1 Permanent Fail:SUV:Threshold
        2. 13.7.2.2 Permanent Fail:SUV:Delay
      3. 13.7.3  Permanent Fail:SOV
        1. 13.7.3.1 Permanent Fail:SOV:Threshold
        2. 13.7.3.2 Permanent Fail:SOV:Delay
      4. 13.7.4  Permanent Fail:TOS
        1. 13.7.4.1 Permanent Fail:TOS:Threshold
        2. 13.7.4.2 Permanent Fail:TOS:Delay
      5. 13.7.5  Permanent Fail:SOCC
        1. 13.7.5.1 Permanent Fail:SOCC:Threshold
        2. 13.7.5.2 Permanent Fail:SOCC:Delay
      6. 13.7.6  Permanent Fail:SOCD
        1. 13.7.6.1 Permanent Fail:SOCD:Threshold
        2. 13.7.6.2 Permanent Fail:SOCD:Delay
      7. 13.7.7  Permanent Fail:SOT
        1. 13.7.7.1 Permanent Fail:SOT:Threshold
        2. 13.7.7.2 Permanent Fail:SOT:Delay
      8. 13.7.8  Permanent Fail:SOTF
        1. 13.7.8.1 Permanent Fail:SOTF:Threshold
        2. 13.7.8.2 Permanent Fail:SOTF:Delay
      9. 13.7.9  Permanent Fail:VIMR
        1. 13.7.9.1 Permanent Fail:VIMR:Check Voltage
        2. 13.7.9.2 Permanent Fail:VIMR:Max Relax Current
        3. 13.7.9.3 Permanent Fail:VIMR:Threshold
        4. 13.7.9.4 Permanent Fail:VIMR:Delay
        5. 13.7.9.5 Permanent Fail:VIMR:Relax Min Duration
      10. 13.7.10 Permanent Fail:VIMA
        1. 13.7.10.1 Permanent Fail:VIMA:Check Voltage
        2. 13.7.10.2 Permanent Fail:VIMA:Min Active Current
        3. 13.7.10.3 Permanent Fail:VIMA:Threshold
        4. 13.7.10.4 Permanent Fail:VIMA:Delay
      11. 13.7.11 Permanent Fail:CFETF
        1. 13.7.11.1 Permanent Fail:CFETF:OFF Threshold
        2. 13.7.11.2 Permanent Fail:CFETF:OFF Delay
      12. 13.7.12 Permanent Fail:DFETF
        1. 13.7.12.1 Permanent Fail:DFETF:OFF Threshold
        2. 13.7.12.2 Permanent Fail:DFETF:OFF Delay
      13. 13.7.13 Permanent Fail:VSSF
        1. 13.7.13.1 Permanent Fail:VSSF:Fail Threshold
        2. 13.7.13.2 Permanent Fail:VSSF:Delay
      14. 13.7.14 Permanent Fail:2LVL
        1. 13.7.14.1 Permanent Fail:2LVL:Delay
      15. 13.7.15 Permanent Fail:LFOF
        1. 13.7.15.1 Permanent Fail:LFOF:Delay
      16. 13.7.16 Permanent Fail:HWMX
        1. 13.7.16.1 Permanent Fail:HWMX:Delay
    8. 13.8 Security
      1. 13.8.1 Security:Settings
        1. 13.8.1.1 Security:Settings:Security Settings
      2. 13.8.2 Security:Keys
        1. 13.8.2.1 Security:Keys:Unseal Key Step 1
        2. 13.8.2.2 Security:Keys:Unseal Key Step 2
        3. 13.8.2.3 Security:Keys:Full Access Key Step 1
        4. 13.8.2.4 Security:Keys:Full Access Key Step 2
    9. 13.9 Data Memory Summary
  15. 15Revision History

12.4 Subcommands with Data

Table 12-23 Subcommands Table
Command Name Access Offset Data Units Type Description
0x0001 DEVICE_NUMBER Sealed: R
Unsealed: R
Full Access: R		 0 Device Number Hex U2 Reports the device number that identifies the product. The data is returned in little-endian format.
0x0002 FW_VERSION Sealed: R
Unsealed: R
Full Access: R		 0 Device Number (Big-Endian) Hex U2 Device number in big-endian format for compatibility with legacy products
2 Firmware Version (Big-Endian) Hex U2 Device firmware major and minor version number (Big-Endian)
4 Build Number (Big-Endian) Hex U2 Firmware build number in big-endian, binary-coded decimal format for compatibility with legacy products
0x0003 HW_VERSION Sealed: R
Unsealed: R
Full Access: R		 0 Hardware Version Hex U2 Reports the device hardware version number.
0x0004 IROM_SIG Sealed: R
Unsealed: R
Full Access: R		 0 Instruction ROM Signature Hex U2 Calculates and reports the device instruction ROM signature.
0x0005 STATIC_CFG_SIG Sealed: R
Unsealed: R
Full Access: R		 0 Static Configuration Signature Hex U2 The lower 15-bits report the signature of static (non-calibration) configuration data memory. If this does not match the stored System Data:Integrity:Config RAM Signature, the MSBit is set.
0x0007 PREV_MACWRITE Sealed: R
Unsealed: R
Full Access: R		 0 Previous Mac Write Hex U2 Reports the previously written MAC command. This is primarily for use by TI software tools to restore any data after performing background operations.
0x0009 DROM_SIG Sealed: R
Unsealed: R
Full Access: R		 0 Data ROM Signature Hex U2 Calculates and reports the device data ROM signature.
0x0035 SECURITY_KEYS Sealed: —
Unsealed: —
Full Access: R/W		 0 Unseal Key Step 1 Hex U2 This is the first word of the security key that must be sent to transition from SEALED to UNSEALED mode.
2 Unseal Key Step 2 Hex U2 This is the second word of the security key that must be sent to transition from SEALED to UNSEALED mode. It must be sent within 5 seconds of the first word of the key and with no other commands in between.
4 Full Access Key Step 1 Hex U2 This is the second word of the security key that must be sent to transition from UNSEALED to FULLACCESS mode.
6 Full Access Key Step 2 Hex U2 This is the second word of the security key that must be sent to transition from UNSEALED to FULLACCESS mode. It must be sent within 5 seconds of the first word of the key and with no other commands in between.
0x0053 SAVED_PF_STATUS Sealed: R
Unsealed: R
Full Access: R		 0 PF Status A Hex U1 Saved Permanent Failure Status A

Bit descriptions can be found in Section 13.5.1.

1 PF Status B Hex U1 Saved Permanent Failure Status B

Bit descriptions can be found in Section 13.5.2.

2 PF Status C Hex U1 Saved Permanent Failure Status D

Bit descriptions can be found in Section 13.5.3.

3 PF Status D Hex U1 Saved Permanent Failure Status D

Bit descriptions can be found in Section 13.5.4.

4 Fuse Flag Hex U1 This is used to track whether or not the fuse has already been blown. This byte is normally zero but is set to 0x72 after the fuse is blown.
0x0057 MANUFACTURINGSTATUS Sealed: R
Unsealed: R
Full Access: R		 0 Manufacturing Status Hex H2 Provides flags for use during manufacturing.

Bit descriptions can be found in Section 13.5.5.

0x0070 MANU_DATA Sealed: R
Unsealed: R
Full Access: R/W		 0 Manufacturer Data 0 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
1 Manufacturer Data 1 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
2 Manufacturer Data 2 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
3 Manufacturer Data 3 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
4 Manufacturer Data 4 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
5 Manufacturer Data 5 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
6 Manufacturer Data 6 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
7 Manufacturer Data 7 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
8 Manufacturer Data 8 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
9 Manufacturer Data 9 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
10 Manufacturer Data 10 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
11 Manufacturer Data 11 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
12 Manufacturer Data 12 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
13 Manufacturer Data 13 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
14 Manufacturer Data 14 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
15 Manufacturer Data 15 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
0x0070 MANU_DATA Sealed: R
Unsealed: R
Full Access: R/W		 16 Manufacturer Data 16 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
17 Manufacturer Data 17 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
18 Manufacturer Data 18 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
19 Manufacturer Data 19 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
20 Manufacturer Data 20 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
21 Manufacturer Data 21 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
22 Manufacturer Data 22 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
23 Manufacturer Data 23 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
24 Manufacturer Data 24 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
25 Manufacturer Data 25 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
26 Manufacturer Data 26 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
27 Manufacturer Data 27 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
28 Manufacturer Data 28 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
29 Manufacturer Data 29 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
30 Manufacturer Data 30 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
31 Manufacturer Data 31 Hex U1 Manufacturer Data Scratchpad. Can be configured to save this data to OTP. Must be in FULLACCESS mode to write.
0x0071 DASTATUS1 Sealed: R
Unsealed: R
Full Access: R		 0 Cell 1 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
4 Cell 1 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
8 Cell 2 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
12 Cell 2 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
16 Cell 3 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
20 Cell 3 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
24 Cell 4 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
28 Cell 4 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
0x0072 DASTATUS2 Sealed: R
Unsealed: R
Full Access: R		 0 Cell 5 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
4 Cell 5 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
8 Cell 6 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
12 Cell 6 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
16 Cell 7 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
20 Cell 7 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
24 Cell 8 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
28 Cell 8 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
0x0073 DASTATUS3 Sealed: R
Unsealed: R
Full Access: R		 0 Cell 9 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
4 Cell 9 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
8 Cell 10 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
12 Cell 10 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
16 Cell 11 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
20 Cell 11 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
24 Cell 12 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
28 Cell 12 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
0x0074 DASTATUS4 Sealed: R
Unsealed: R
Full Access: R		 8 Cell 13 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
12 Cell 13 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
24 Cell 14 Voltage Counts — I4 32-bit ADC counts for cell voltage measurement.
28 Cell 14 Current Counts — I4 32-bit ADC counts for current measurement taken during the cell voltage measurement.
0x0075 DASTATUS5 Sealed: R
Unsealed: R
Full Access: R		 0 VREG18 — I2 16-bit ADC count of the VREG18 measurement, which is used as a proxy to check the coulomb counter reference voltage. This is measured for diagnostic purposes.
2 VSS — I2 16-bit ADC count of the VSS pin. This is measured for diagnostic purposes to ensure the ADC input mux is working properly.
4 Max Cell Voltage mV I2 Maximum Cell Voltage
6 Min Cell Voltage mV I2 Minimum Cell Voltage
8 Battery Voltage Sum userV I2 Sum of cell voltages (including interconnects). This can be compared to the Stack Voltage() for diagnostic purposes. Note, however, that these measurements are taken at different times which may cause variation.
10 Cell Temperature 0.1K I2 Reports the cell temperature being used for features depending on a single temperature threshold. Note many features (such as protections) use minimum or maximum cell temperature instead.
12 FET Temperature 0.1K I2 Reports the FET temperature given by the maximum of all measured FET temperatures.
14 Max Cell Temperature 0.1K I2 Reports the maximum of all measured cell temperatures.
16 Min Cell Temperature 0.1K I2 Reports the minimum of all measured cell temperatures.
18 Avg Cell Temperature 0.1K I2 Reports the average of all measured cell temperatures.
20 CC3 Current userA I2 Reports the CC3 Current, which is obtained by averaging a configurable number of CC2 current measurements.
22 CC1 Current userA I2 Reports the CC1 current, which is updated every 250 ms in NORMAL mode. In SLEEP mode, this is updated every 4 seconds beginning one second after voltage measurements end. See the documentation on power modes for further details.
24 CC2 Counts — I4 Raw 32-bit count value for the latest CC2 measurement.
28 CC3 Counts — I4 Raw 32-bit count value for the latest CC3 measurement.
0x0076 DASTATUS6 Sealed: R
Unsealed: R
Full Access: R		 0 Accum Charge userAh I4 Reports the integer portion of accumulated passed charge in userAmp-hours.
4 Accum Charge Fraction — U4 Reports the fractional portion of accumulated passed charge. This is initialized to 0.5 userAh to facilitate appropriate rounding of the integer portion.
8 Accum Time s U4 Reports the number of seconds over which passed charge has been integrated.
12 CFETOFF Counts — I4 Reports the 32-bit ADC counts for the most recent measurement on the CFETOFF pin.
16 DFETOFF Counts — I4 Reports the 32-bit ADC counts for the most recent measurement on the DFETOFF pin.
20 ALERT Counts — I4 Reports the 32-bit ADC counts for the most recent measurement on the ALERT pin.
24 TS1 Counts — I4 Reports the 32-bit ADC counts for the most recent measurement on the TS1 pin.
28 TS2 Counts — I4 Reports the 32-bit ADC counts for the most recent measurement on the TS2 pin.
0x0077 DASTATUS7 Sealed: R
Unsealed: R
Full Access: R		 0 TS3 Counts — I4 Reports the 32-bit ADC counts for the most recent measurement on the TS3 pin.
4 HDQ Counts — I4 Reports the 32-bit ADC counts for the most recent measurement on the HDQ pin.
8 DCHG Counts — I4 Reports the 32-bit ADC counts for the most recent measurement on the DCHG pin.
12 DDSG Counts — I4 Reports the 32-bit ADC counts for the most recent measurement on the DDSG pin.
0x0080 CUV_SNAPSHOT Sealed: R
Unsealed: R
Full Access: R		 0 Cell 1 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
2 Cell 2 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
4 Cell 3 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
6 Cell 4 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
8 Cell 5 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
10 Cell 6 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
12 Cell 7 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
14 Cell 8 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
16 Cell 9 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
18 Cell 10 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
20 Cell 11 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
22 Cell 12 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
26 Cell 13 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
30 Cell 14 Voltage at CUV Event mV I2 Records the cell voltage measurement made just after the latest CUV event.
0x0081 COV_SNAPSHOT Sealed: R
Unsealed: R
Full Access: R		 0 Cell 1 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
2 Cell 2 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
4 Cell 3 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
6 Cell 4 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
8 Cell 5 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
10 Cell 6 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
12 Cell 7 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
14 Cell 8 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
16 Cell 9 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
18 Cell 10 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
20 Cell 11 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
22 Cell 12 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
26 Cell 13 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
30 Cell 14 Voltage at COV Event mV I2 Records the cell voltage measurement made just after the latest COV event.
0x0083 CB_ACTIVE_CELLS Sealed: R/W
Unsealed: R/W
Full Access: R/W		 0 Cell Balancing Active Cells — U2 When read, reports a bit mask of which cells are being actively balanced. When written, starts balancing on the specified cells. Bits 0‒11 correspond to cell-1 through cell-12. Bit 13 corresponds to cell-13, bit 15 corresponds to cell-14. Bits 12 and 14 should only be written with a "0".Write 0x0000 to turn all balancing off.
0x0084 CB_SET_LVL Sealed: W
Unsealed: W
Full Access: W		 0 Cell Balancing Set Level mV I2 Start balancing cells that are above the written voltage threshold. This will not balance adjacent cells or more cells than the programmed limit.
0x0085 CBSTATUS1 Sealed: R
Unsealed: R
Full Access: R		 0 Cell Balancing Present Time s U2 Reports the number of seconds that balancing has been continuously active.
0x0086 CBSTATUS2 Sealed: R
Unsealed: R
Full Access: R		 0 Cell 1 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
4 Cell 2 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
8 Cell 3 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
12 Cell 4 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
16 Cell 5 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
20 Cell 6 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
24 Cell 7 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
28 Cell 8 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
0x0087 CBSTATUS3 Sealed: R
Unsealed: R
Full Access: R		 0 Cell 9 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
4 Cell 10 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
8 Cell 11 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
12 Cell 12 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
20 Cell 13 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
28 Cell 14 Total Balancing Time s U4 Reports the cumulative number of seconds that balancing has been active on this cell since the last device reset.
0x0097 FET_CONTROL Sealed: W
Unsealed: W
Full Access: W		 0 FET Control Hex H1 Allows host control of individual FET drivers. This subcommand should not be used if the DDSG or DCHG pin is being used in DDSG/DCHG mode.

Bit descriptions can be found in Section 13.5.6.

0x0098 REG12_CONTROL Sealed: W
Unsealed: W
Full Access: W		 0 REG12 Control Hex H1 Changes voltage regulator settings

Bit descriptions can be found in Section 13.5.7.

0x00a0 OTP_WR_CHECK Sealed: —
Unsealed: R
Full Access: R		 0 OTP Write Check Result Hex H1 Reports whether or not OTP programming is allowed.

Bit descriptions can be found in Section 13.5.8.

1 OTP Write Check Data Fail Addr Hex U2 When data cannot be programmed to OTP because no XOR bits remain, this will contain the address of the first data value which could not be programmed.
0x00a1 OTP_WRITE Sealed: —
Unsealed: R
Full Access: R		 0 OTP Write Result Hex H1 Reports whether or not OTP programming is allowed.

Bit descriptions can be found in Section 13.5.9.

1 OTP Write Data Fail Addr Hex U2 When data cannot be programmed to OTP because no XOR bits remain, this will contain the address of the first data value which could not be programmed.
0xf081 READ_CAL1 Sealed: —
Unsealed: R
Full Access: R		 0 Calibration Data Counter — I2 Sample counter that is incremented when buffer is updated. Used to ensure unique measurement samples are taken when averaging is required.
2 CC2 Counts — I4 32-bit CC2 Counts from the most recent current measurement.
6 PACK pin ADC Counts — I2 16-bit ADC counts from previous PACK pin voltage measurement.
8 Top of Stack ADC Counts — I2 16-bit ADC counts from previous Top of Stack voltage measurement.
10 LD pin ADC Counts — I2 16-bit ADC counts from previous Top of Stack voltage measurement.
0xf090 CAL_CUV Sealed: —
Unsealed: R
Full Access: R		 0 CUV Threshold Override Hex U2 Calibrates CUV using the top cell input to set Calibration:COV:COV Threshold Override. By using this calibration command, threshold levels between the normal 50-mV steps can be set. Only available in CONFIG_UPDATE mode.
0xf091 CAL_COV Sealed: —
Unsealed: R
Full Access: R		 0 COV Threshold Override Hex U2 Calibrates COV using the top cell input to set Calibration:COV:COV Threshold Override. By using this calibration command, threshold levels between the normal 50-mV steps can be set. Only available in CONFIG_UPDATE mode.
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