SLVAE22A July 2018 – March 2019 TPS54334 , TPS65251 , TPS65251-1 , TPS65251-2 , TPS65251-3 , TPS652510 , TPS65261 , TPS65263 , TPS65263-1Q1 , TPS65263-Q1 , TPS65265 , TPS65266 , TPS65266-1 , TPS65270 , TPS65273V , TPS65276V , TPS65279 , TPS65279V
2 Unified PCM BUCK Converter
Figure 1 shows a PCM Buck converter, which is usually composed of several key blocks. It includes the following:
- Error Amplifier (EA)
- PWM Comparator (PWM)
- Slope Compensation (SLP)
- Current Sensing (CS)
- Clock (CLK)
- Power Stage
- Output Stage
The RC network after error amplifier compensates for the output pole and increases loop gain for stability. Typically, Figure 1 can explain PCM BUCK converters.
Figure 1. PCM BUCK Converter Block Diagram During normal operation, the voltage difference between the internal reference voltage (Vref) and the feedback voltage (VFB) is amplified and outputs at COMP node. The clock signal (CLK) turns on high-side FET. The sensed current (CS) compares with the COMP voltage minus slope compensation (SLP) and the output logic is set to turn off high-side FET. The low-side FET turns on for the rest of the period.
Assuming the operating frequency is fixed, the slope compensation is linear, and the COMP is a pin that you can use to measure its voltage at this node. The whole application is explained based on this unified PCM model in CCM (Continuous Current Mode).