SLVAEJ5C February 2020 – December 2020 TPS62810-Q1 , TPS62811-Q1 , TPS62812-Q1 , TPS62813-Q1
This section provides a Failure Mode Analysis (FMA) for the pins of the TPS6281x-Q1. The failure modes covered in this document include the typical pin-by-pin failure scenarios:
Table 4-2 through Table 4-5 also indicate how these pin conditions can affect the device as per the failure effects classification in Table 4-1.
Class | Failure Effects |
---|---|
A | Potential device damage that affects functionality |
B | No device damage, but loss of functionality |
C | No device damage, but performance degradation |
D | No device damage, no impact to functionality or performance |
Figure 4-1 shows the pin diagram. For a detailed description of the device pins please refer to the 'Pin Configuration and Functions' section in the TPS6281x-Q1 datasheet.
Following are the assumptions of use and the device configuration assumed for the pin FMA in this section:
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
MODE/SYNC | 1 | Intended functionality. | D |
VIN | 2 | Device does not power up. | B |
SW | 3 | Potential device damage. | A |
GND | 4 | No effect. | D |
FB | 5 | Output voltage regulated to VIN (100% mode). | B |
SS/TR | 6 | Device not functional. | B |
COMP/FSET | 7 | Intended functionality. | D |
EN | 8 | Intended functionality. | D |
PG | 9 | Intended functionality. | D |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
MODE/SYNC | 1 | Undetermined device operation. | B |
VIN | 2 | Device does not power up. | B |
SW | 3 | Device not functional, open loop operation. | B |
GND | 4 | Device not functional. | B |
FB | 5 | Undetermined output voltage behavior; open loop operation. | B |
SS/TR | 6 | Intended functionality. | D |
COMP/FSET | 7 | Intended functionality. | D |
EN | 8 | Undetermined device operation; device might power up or not. | B |
PG | 9 | Intended functionality. | B |
Pin Name | Pin No. | Shorted to | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|---|
MODE/SYNC | 1 | PG | Device runs FPWM mode once PG is high impedance. | B |
FB | 5 | SS/TR | Undetermined device operation, VOUT spikes up to VIN | B |
SS/TR | 6 | COMP/FSET | Undetermined device operation. | B |
EN | 8 | PG | Device does not power up. | B |
Pin Name | Pin No. | Description of Potential Failure Effect(s) | Failure Effect Class |
---|---|---|---|
MODE/SYNC | 1 | Intended functionality: Forced PWM. | D |
VIN | 2 | Intended functionality. | D |
SW | 3 | Potential device damage. | A |
GND | 4 | Device does not power up. | B |
FB | 5 | Potential device damage. | A |
SS/TR | 6 | Intended functionality. | D |
COMP/FSET | 7 | Intended functionality. | D |
EN | 8 | Intended functionality. | D |
PG | 9 | Potential device damage. | A |