SLVAEQ3A February 2020 – July 2020 TPS25840-Q1 , TPS25842-Q1
The failure mode distribution estimation for TPS25840-Q1 and TPS25842-Q1 in Table 3-1 comes from the combination of common failure modes listed in standards such as IEC 61508 and ISO 26262, the ratio of sub-circuit function size and complexity and from best engineering judgment.
The failure modes listed in this section reflect random failure events and do not include failures due to misuse or overstress.
| Die Failure Modes | Failure Mode Distribution (%) |
|---|---|
| SW no output | 25% |
| CSN/OUT not in specification – voltage or timing | 20% |
| LS/GD no output | 5% |
| LS/GD not in specification – voltage or timing | 5% |
| DP_IN, DM_IN, DP_OUT, DM_OUT no output | 15% |
| DP_IN, DM_IN, DP_OUT, DM_OUT not in specification – voltage or timing | 20% |
| FAULT, BUCK_ST false trip or fails to trip | 5% |
| Short circuit any two pins | 5% |